Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9836567-B2
Application number	US-201214424212-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 14, 2012
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.

First claim

The invention claimed is:

1. A method for optimizing performance of a semiconductor integrated circuit, the method comprising:
generating from a behavioral description of the semiconductor integrated circuit, a high level description of said semiconductor integrated circuit, in which the semiconductor integrated circuit is partitioned into sub-modules, each sub-module including at least one register;
generating, from the high level description of the semiconductor integrated circuit, a low level description of the semiconductor integrated circuit comprising a plurality of instances describing operation of the semiconductor integrated circuit, in which the plurality of instances respectively describe logically interconnected functional units including standard cells and other functional units different from said standard cells;
retrieving, from a technology library, metrics values respectively associated with each instance of the low level description of the semiconductor integrated circuit;
conducting a low level function analysis of the semiconductor integrated circuit based on said metrics values;
performing a design optimization comprising first mapping the metrics values of instances describing, in the low level description of the semiconductor integrated circuit, functional units different from the standard cells, to standard cells logically connected to said instances, by dividing each of said instance metrics values between standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metrics value to the metrics value of each of said standard cells logically connected to said corresponding instance, second mapping the metrics values respectively associated with each standard cell of the low level description of the semiconductor integrated circuit to a corresponding register of the high level description of the integrated circuit, based on the first mapping, and determining metrics values respectively associated with the sub-modules based on the second mapping;
generating an optimized layout of the semiconductor integrated circuit based upon the determined metrics values; and
fabricating the semiconductor integrated circuit based upon the optimized layout.

2. The method of claim 1 , wherein the first mapping is performed by dividing the metrics value of the instance equally between all the flip-flops logically connected to said instance.

3. The method of claim 1 , wherein, in the high level description of the semiconductor integrated circuit, said integrated circuit is partitioned into sub-modules at least some of which including a plurality of registers logically associated according to a hierarchy, and wherein for every sub-module of the low level description of the integrated circuit, the determining of the metrics value of the sub-module comprises setting said metrics value as the sum of respective metrics values of all registers of the sub-module in the hierarchy.

4. The method of claim 1 , wherein in the high level description of the semiconductor integrated circuit, said integrated circuit is partitioned into sub-modules at least some of which including a plurality of registers logically associated according to a hierarchy with at least one sub-hierarchy, for every sub-module of the low level description of the integrated circuit, the determining of the metrics value of the sub-module comprises setting said metrics value as the sum of respective metrics values of all registers of the sub-module in the hierarchy and in every sub-hierarchy of said hierarchy.

5. The method of claim 1 , wherein the high level description of the semiconductor integrated circuit comprises a Register Transfer Level (RTL) description in which the semiconductor integrated circuit is partitioned into sub-modules, each sub-module including RTL registers.

6. The method of claim 1 , wherein the low level description of the semiconductor integrated circuit comprises a Gate Level (GL) net list having instances describing the operation of the semiconductor integrated circuit.

7. The method of claim 1 , wherein the metrics values include power consumption values respectively associated with each instance of the low level description of the semiconductor integrated circuit.

8. The method of claim 7 , wherein the first mapping comprises dividing the instance metrics values of each of the instances between standard cells logically connected to the corresponding instance substantially equally between at least one drive standard cell and at least one load standard cell to which said corresponding instance is logically connected.

9. The method of claim 1 , wherein the standard cells are flip-flops.

10. A computer program product embodied on a non-transitory computer readable medium comprising computer readable code which, when implemented on a design processor causes the design processor to perform the method according to claim 1 .

11. A design processor configured to optimize performance of a semiconductor integrated circuit comprising:
a high level synthesizer configured to generate, from a behavioral description of the semiconductor integrated circuit, a high level description of said semiconductor integrated circuit, in which the semiconductor integrated circuit is partitioned into sub-modules, each sub-module including at least one register;
a low level synthesizer configured to generate, from the high level description of the semiconductor integrated circuit, a low level description of the semiconductor integrated circuit comprising a plurality of instances describing operation of the semiconductor integrated circuit, in which the plurality of instances respectively describe logically interconnected functional units including standard cells and other cells different from said standard cells;
a low level function simulation unit configured to retrieve, from a technology library, metrics values respectively associated with each instance of the low level description of the semiconductor integrated circuit, and to conduct a low level function analysis of the semiconductor integrated circuit based on said metrics values;
a design optimization unit configured to perform a first mapping of the metrics values of instances describing, in the low level description of the semiconductor integrated circuit, functional units different from the standard cells, to standard cells logically connected to said instances, by dividing each of said instance metrics values between standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metrics value to the metrics value of each of said standard cells logically connected to said corresponding instance, a second mapping of the metrics values respectively associated with each standard cell of the low level description of the semiconductor integrated circuit to a corresponding register of the high level description of the integrated circuit, based on the first mapping, and a determination of the metrics values respectively associated to the sub-modules, based on the second mapping; and
a layout unit configured to generate an optimized layout of the semiconductor integrated circuit based upon the determined metrics values; and
a tape output unit configured to fabricate the semiconductor integrated circuit based upon the optimized layout.

12. The design processor of claim 11 , wherein the first mapping is done by dividing the metrics value of the instance equally between all the flip-flops logically connected to said instance.

13. The design processor of claim 11 , wherein, in the high level description of the semiconductor integrated circuit, sai

Assignees

• Berkovitz Asher
• Magini Uzi
• Priel Michael
• Nxp Usa Inc

Inventors

• Berkovitz Asher
• Magini Uzi
• Priel Michael

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2111/06

  Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] · CPC title

• Y02T10/82

  Elements for improving aerodynamics · CPC title