Processor memory system

Patent metadata

Field	Value
Publication number	US-9836412-B2
Application number	US-201514707166-A
Country	US
Kind code	B2
Filing date	May 8, 2015
Priority date	Aug 13, 2004
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.

First claim

The invention claimed is:

1. A multiprocessor system, comprising:
a plurality of processing elements having a corresponding plurality of physical local memories, the plurality of processing elements including a first processing element having a first physical local memory and a first processor, and a second processing element having a second physical local memory;
a packet-switched interconnection network to receive memory addresses from each of the plurality of processing elements, the interconnection network also to couple each of the plurality of processing elements to a respective corresponding physical local memory for accessing data stored therein, the interconnection network also to couple each of the plurality of processing elements to each of the physical local memories of other of the plurality of processing elements for accessing data stored therein;
the first processing element to reference a first memory location in the first physical local memory by passing, to the interconnection network, a first global memory address formed by combining the physical location in the first physical local memory, a first identifier associated with the first processing element, and a first processor identifier associated with the first processor;
the first processing element to reference a second memory location in the second physical local memory by passing, to the interconnection network, a second global memory address formed by combining, in the same manner as the first global memory address was formed, the physical location in the second physical local memory, a second identifier associated with the second processing element, and the first processor identifier.

2. The multiprocessor system of claim 1 , wherein a first range of addresses passed to the interconnection network by each of the plurality of processing elements is referencing memory locations in the physical local memory of the respective processing element.

3. The multiprocessor system of claim 2 , wherein a second range of addresses passed to the interconnection network by each of the plurality of processing elements is referencing memory locations in the physical local memory of a different processing element.

4. The multiprocessor system of claim 3 , wherein the first range of addresses and the second range of addresses are contiguous.

5. The multiprocessor system of claim 1 , wherein the second processing element includes a second processor.

6. The multiprocessor system of claim 3 , wherein a third range of addresses between the first range of addresses and the second range of addresses reference to an external shared memory.

7. A method of accessing local memories in a multi-processor system having an interconnection network, comprising:
referencing, by a plurality of processing elements that include a corresponding plurality of physical local memories, memory locations by passing global memory addresses to the interconnection network, the global memory addresses formed by combining a physical location in a physical local memory, an identifier associated with a processing element that includes the physical local memory, and a processor identifier associated with a processor;
receiving global memory addresses from each of the plurality of processing elements;
based on a first plurality of global memory addresses that include an identifier associated with a processing element that is making the access, coupling each of the plurality of processing elements to a respective corresponding physical local memory of the processing element making the access for accessing data stored therein; and,
based on a second plurality of global memory addresses that include identifiers associated with processing elements that are not making the access, coupling each of the plurality of processing elements to each of the physical local memories of processing elements that are not making the access for accessing data stored therein.

8. The method of claim 7 , wherein the interconnect network includes and an end node coupled to an external memory.

9. The method of claim 8 , wherein the external memory comprises non-local shared memory.

10. The method of claim 7 , wherein a first range of addresses passed to the interconnection network by each of the plurality of processing elements references memory locations in the physical local memory of the respective processing element.

11. The method of claim 10 , wherein a second range of addresses passed to the interconnection network by each of the plurality of processing elements references memory locations in the physical local memory of a different processing element.

12. The method of claim 11 , wherein the first range of addresses and the second range of addresses are contiguous.

13. The method of claim 11 wherein the first range of addresses and the second range of addresses are non-contiguous.

14. The method of claim 11 , wherein a third range of addresses between the first range of addresses and the second range of addresses reference to an external shared memory.

15. A packet-switched interconnection network, comprising:
a first at least one interface to a plurality of processing elements having a corresponding plurality of physical local memories, the plurality of processing elements including a first processing element having a first physical local memory and a first processor, and a second processing element having a second physical local memory, the interconnection network also to couple each of the plurality of processing elements to a respective corresponding physical local memory for accessing data stored therein, the interconnection network also to couple each of the plurality of processing elements to each of the physical local memories of other of the plurality of processing elements for accessing data stored therein;
the first processing element to reference a first memory location in the first physical local memory by passing, to the first at least one interface, a first global memory address formed by combining the physical location in the first physical local memory, a first identifier associated with the first processing element, and a first processor identifier associated with the first processor;
the first processing element to reference a second memory location in the second physical local memory by passing, to the first at least one interface, a second global memory address formed by combining, in the same manner as the first global memory address was formed, the physical location in the second physical local memory, a second identifier associated with the second processing element, and the first processor identifier; and,
a second at least one interface to couple the interconnection network to an external memory.

16. The interconnection network of claim 15 , wherein a first range of addresses passed to the interconnection network by each of the plurality of processing elements is to reference memory locations in the physical local memory of the respective processing element.

17. The interconnection network of claim 16 , wherein a second range of addresses passed to the interconnection network by each of the plurality of processing elements is to reference memory locations in the physical local memory of a different processing element.

18. The interconnection network of claim 17 , wherein the first range of addresses and the second range of addresses are contiguous.

19. The interconnection network of claim 17 , wherein the first range of addresses and the second range of addresses are non-contiguous.

20. The

Assignees

• Rambus Inc

Inventors

• Mcconnell Ray

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F15/8015 Primary

  One dimensional arrays, e.g. rings, linear arrays, buses · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F15/17337

  Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004) · CPC title

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title