Selectable reconfiguration for dynamically reconfigurable IP cores

Patent metadata

Field	Value
Publication number	US-9633158-B1
Application number	US-201414538784-A
Country	US
Kind code	B1
Filing date	Nov 11, 2014
Priority date	Nov 11, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.

First claim

What is claimed is:

1. A method to implement reconfiguration of a hardened intellectual property (IP) block of an integrated circuit (IC) that includes a programmable logic fabric, comprising:
receiving one or more pre-configured profiles that provide one or more distinct configurations of the hardened IP block;
generating configuration data associated with each of the distinct configurations of the hardened IP block;
designating configuration storage space to store the configuration data; and
generating reconfiguration control logic to be implemented on the programmable logic fabric of the IC, wherein the reconfiguration control logic reads the configuration data and programs the hardened IP block with the configuration data.

2. The method of claim 1 , wherein the configuration data comprises register settings of the hardened IP block.

3. The method of claim 1 , comprising:
determining similarities between the configuration data of the distinct configurations; and
reconfiguring only portions of the hardened IP block that are dissimilar.

4. The method of claim 1 , wherein the hardened IP block comprises configurable sets of registers.

5. The method of claim 1 , wherein designating the configuration storage space to store the configuration data comprises designating storage areas on read-only memory (ROM).

6. The method of claim 1 , comprising:
receiving commands selecting one or more of the pre-configured profiles; and
reconfiguring the hardened IP block with the one or more pre-configured profiles.

7. The method of claim 1 , comprising generating user reconfiguration logic that links user input to the reconfiguration control logic.

8. The method of claim 1 , comprising programming the configuration data to the hardened IP block via a reconfiguration interface.

9. The method of claim 1 , comprising reconfiguring the hardened IP block to change a functionality of the hardened IP block.

10. The method of claim 1 , wherein the method is configured to be carried out on an integrated circuit (IC) device, comprising:
one or more of the hardened intellectual property (IP) blocks reconfigurable at runtime via one or more of the pre-configured profiles; and
one or more interface ports that receive the pre-configured profiles to reconfigure the hardened IP blocks during runtime, wherein the pre-configured profiles are selected and implemented via the reconfiguration control logic.

11. The method of claim 10 , wherein the method is configured to be carried out on the IC device comprising a memory device that stores the one or more pre-configured profiles.

12. The method of claim 10 , wherein the method is configured to be carried out on the IC device comprising a memory device that stores the one or more pre-configured profiles and the control logic.

13. The method of claim 10 , wherein the pre-configured profiles are associated with register settings of the hardened IP blocks.

14. A method to implement reconfiguration of a hardened intellectual property (IP) block of an integrated circuit (IC) that includes a programmable logic fabric, comprising:
receiving one or more pre-configured profiles providing configurations of the hardened IP block;
generating configuration data from the pre-configured profiles;
generating an IP hardware description language (HDL) module that stores the configuration data and generates reconfiguration control logic to be implemented on the programmable fabric of the IC, wherein the reconfiguration control logic reads the configuration data and implements the configuration data in the hardened IP block; and
receiving and implementing the configuration data at the hardened IP block provided by the reconfiguration control logic.

15. The method of claim 14 , wherein generating the configuration data comprises generating register settings associated with the hardened IP block from the pre-configured profiles.

16. The method of claim 14 , wherein generating register settings comprises generating register settings of a set of registers associated with each of the pre-configured profiles.

17. The method of claim 16 , wherein implementing the configuration data comprises reconfiguring only registers of the set of registers that are configured differently from the register settings of the configuration of the hardened IP block implemented immediately prior to reconfiguration.

18. The method of claim 14 , wherein generating the IP HDL module comprises compiling the IP HDL in a single instance.

19. The method of claim 14 , comprising:
receiving a signal from a reconfiguration input; and
selecting from the pre-configured profiles based on the signal from the reconfiguration input.

20. A method to implement reconfiguration of a hardened intellectual property (IP) block of an integrated circuit (IC) that includes a programmable logic fabric, comprising:
receiving one or more pre-configured profiles that provide one or more configurations of the hardened IP block;
generating configuration data associated with the one or more configurations of the hardened IP block;
generating an IP hardware description language (HDL) module that implements storage to store the configuration data and generates reconfiguration control logic to be implemented on the programmable fabric of the IC, wherein the reconfiguration control logic reads the configuration data and programs the hardened IP block with the configuration data.

21. The method of claim 10 , wherein the pre-configured profiles are selected via control logic based on instructions received from a reconfiguration input.

Assignees

• Altera Corp

Inventors

• Jones Jakob Raymond
• Padmanabhan Prasanna

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• G06F15/8015

  One dimensional arrays, e.g. rings, linear arrays, buses · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title