Arrangement and method for checking the entropy of a random number sequence

Patent metadata

Field	Value
Publication number	US-9836280-B2
Application number	US-201615045277-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Feb 19, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

According to one embodiment, an arrangement for checking the entropy of a random number sequence is described including a random source configured to provide a random input sequence, a post-processing circuit configured to receive the random input sequence and to generate a random number sequence from the random input sequence by performing a post-processing and a decimation of the random input sequence, an inverse post-processing circuit configured to receive the random number sequence from the post-processing circuit and to generate a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit, and an entropy checker configured to check the entropy of the random number sequence based on the processed random number sequence.

First claim

What is claimed is:

1. An arrangement for checking the entropy of a random number sequence comprising:
a random source configured to provide a random input sequence;
a post-processing circuit configured to receive the random input sequence and to generate a random number sequence from the random input sequence by performing a post-processing and a decimation of the random input sequence;
an inverse post-processing circuit configured to receive the random number sequence from the post-processing circuit and to generate a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit; and
an entropy checker configured to check the entropy of the random number sequence based on the processed random number sequence.

2. The arrangement of claim 1 ,
wherein the decimation includes outputting a first number of post-processed bits for every second number of bits of the random input sequence input into the post-processing circuit.

3. The arrangement of claim 1 ,
wherein the decimation is a compression of the random input sequence by a compression factor equal to a power of 2.

4. The arrangement of claim 1 ,
wherein the post-processing circuit comprises a linear feedback shift register and the post-processing is a processing of the random input sequence by the linear feedback shift register.

5. The arrangement of claim 4 ,
wherein the decimation includes outputting a first number of bits stored in the linear feedback shift register each time after a second number of bits of the random input sequence have been input into the linear feedback shift register.

6. The arrangement of claim 4 ,
wherein the inverse post-processing circuit comprises a further linear feedback shift register and the processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit is a processing of the random number sequence by the further linear feedback shift register.

7. The arrangement of claim 6 ,
wherein the linear feedback shift register and the further linear feedback shift register are configured according to the same primitive polynomial.

8. The arrangement of claim 1 ,
wherein the random source comprises a noise source and a digitization unit configured to generate the random input sequence by digitizing noise output by the noise source.

9. The arrangement of claim 1 ,
wherein the entropy checker is configured to detect whether the entropy of the random number sequence is zero and, if it has detected that the entropy of the processed random number sequence is zero, to output a signal indicating that the random source has failed.

10. The arrangement of claim 1 ,
wherein the entropy checker is configured to detect whether the entropy of the processed random number sequence is zero by detecting whether the processed random number sequence is constant.

11. The arrangement of claim 1 , further comprising:
a controller configured to check the integrity of the post-processing circuit by checking whether the processed random number sequence is constant in response to a constant random input sequence.

12. The arrangement of claim 1 ,
wherein the entropy checker is configured to measure the entropy of the random number sequence by measuring the entropy of the processed random number sequence.

13. The arrangement of claim 12 ,
wherein the entropy checker is configured to measure the entropy of the processed random number sequence by applying a statistical test to the processed random number sequence.

14. A processing device, comprising;
an arrangement for checking the entropy of a random number sequence, comprising:
a random source configured to provide a random input sequence;
a post-processing circuit configured to receive the random input sequence and to generate a random number sequence from the random input sequence by performing a post-processing and a decimation of the random input sequence;
an inverse post-processing circuit configured to receive the random number sequence from the post-processing circuit and to generate a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit; and
an entropy checker configured to check the entropy of the random number sequence based on the processed random number sequence.

15. The processing device of claim 14 ,
wherein the processing device is a chip card.

16. A method for checking the entropy of a random number sequence comprising:
generating a random number sequence from a random input sequence by performing a post-processing and a decimation of the random input sequence;
generating a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing; and
checking the entropy of the random number sequence based on the processed random number sequence.

17. The method of claim 16 ,
wherein the decimation includes outputting a first number of post-processed bits for every second number of bits of the random input sequence input into the post-processing circuit.

18. The method of claim 16 ,
wherein the decimation is a compression of the random input sequence by a compression factor equal to a power of 2.

19. The method of claim 16 , further comprising:
checking the integrity of the post-processing circuit by checking whether the processed random number sequence is constant in response to a constant random input sequence.

20. The method of claim 16 ,
wherein the method is performed by a chip card.

Assignees

• Infineon Technologies Ag

Inventors

• Bucci Marco
• Luzzi Raimondo

Classifications

• G06F7/584 Primary

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• G16Z99/00

  Subject matter not provided for in other main groups of this subclass · CPC title