Semiconductor memory device and random number generator

Patent metadata

Field	Value
Publication number	US-9280317-B2
Application number	US-201313945186-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	May 13, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

According to one embodiment, semiconductor memory device and a random number generator includes A semiconductor memory device includes: a semiconductor memory 30 , a random number generator 10 generating a random number sequence, and a data writing unit 20 storing data in the semiconductor memory 30 using the random number sequence. The random number generator 10 includes: a random number generating unit generating an M-bit random number sequence; a coefficient selecting unit outputs a first coefficient or a second coefficient to the random number generating unit; and a bit selecting unit which outputs the random number sequence obtained by selecting N bits from M-bit random number sequence output from the random number generating unit.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor memory;
a random number generator configured to generate, when storing data in the semiconductor memory, a random number sequence for randomizing the data using an address value of the data to be stored in the semiconductor memory; and
a data writing circuit configured to store, in the semiconductor memory, the randomized data using the random number sequence generated by the random number generator, the random number generator including
M (M is a positive integer) number of shift registers, having a feedback loop for a part of the M shift registers, and generating an M-bit random number sequence,
a coefficient selecting circuit that, when generation of the random number sequence in the random number generator is started, selects, on the basis of a first value, one of a plurality of first coefficient groups for activating or deactivating the feedback loop and outputs the selected one of the plurality of first coefficient groups as a first coefficient to the random number generator, and that, when the generation of the random number sequence in the random number generator is continued, outputs a second coefficient different from the first coefficient, the second coefficient being for activating or deactivating the feedback loop, the first value being generated from a group of bits of the address value of the data to be stored in the semiconductor memory, and
a bit selecting circuit that selects one from a plurality of selection patterns on the basis of a second value that is generated from, among the address value of the data to be stored in the semiconductor memory, a group of bits different from the group of bits from which the first value is generated, and that outputs a random number sequence obtained by selecting N (N is a positive integer satisfying M≧N) bits from the M-bit random number sequence output from the random number generator in accordance with the selected selection pattern.

2. The semiconductor memory device of claim 1 , wherein:
the first value is a value that is generated, when a number of the first coefficient groups is two to an X-th power (X is a positive integer), using an X number of bits among the address value of the data; and
the second value is a value that is generated, when a number of the second coefficient groups is two to a Y-th power (Y is a positive integer), using a Y number of bits among the address value of the data, the Y number of bits being different from the X number of bits.

3. The semiconductor memory device of claim 2 , wherein, when a bit position with a value of 0 exists in both the first coefficient and the second coefficient, the random number generator does not set the feedback loop corresponding to the bit position.

4. The semiconductor memory device of claim 2 , wherein, when the random number sequence is generated using the first value, the second value, and frequency of access to a destination address value in the semiconductor memory to which the data is to be stored:
the coefficient selecting circuit selects, on the basis of the first value and a third value, one of coefficient groups greater in number than a number of the plurality of first coefficient groups, and outputs the selected one of coefficient groups, the third value being generated from a group of bits of the frequency of access; and
the bit selecting circuit selects, on the basis of the second value and a fourth value, one of selection patterns greater in number than a number of the plurality of selection patterns, and selects N bits in accordance with the selected pattern, and outputs a random number sequence, the fourth value being generated from, among the frequency of access, a group of bits different from the group of bits from which the third value is generated.

5. The semiconductor memory device of claim 2 , wherein:
the coefficient selecting circuit includes a first selector and a second selector;
the first selector, when the generation of the random number sequence in the random number generator is started, selects, on the basis of the first value, one of the plurality of first coefficient groups for activating or deactivating the feedback loop, and outputs the selected one of the plurality of first coefficient groups to the second selector, the first value being generated from the group of bits of the address value of the data to be randomized by the random number sequence; and
the second selector, when the generation of the random number sequence in the random number generator is started, outputs the first coefficient input from the first selector to the random number generator, and when the generation of the random number sequence in the random number generator is continued, outputs the second coefficient to the random number generator.

6. The semiconductor memory device of claim 1 , wherein, when a bit position with a value of 0 exists in both the first coefficient and the second coefficient, the random number generator does not set the feedback loop corresponding to the bit position.

7. The semiconductor memory device of claim 1 , wherein, when the random number sequence is generated using the first value, the second value, and frequency of access to a destination address value in the semiconductor memory to which the data is to be stored,
the coefficient selecting circuit selects, on the basis of the first value and a third value, one of coefficient groups greater in number than a number of the plurality of first coefficient groups, and outputs the selected one of coefficient groups, the third value being generated from a group of bits of the frequency of access, and
the bit selecting circuit selects, on the basis of the second value and a fourth value, one of selection patterns greater in number than a number of the plurality of selection patterns and selects N bits in accordance with the selected pattern, and outputs a random number sequence, the fourth value being generated from, among the frequency of access, a group of bits different from the group of bits from which the third value is generated.

8. The semiconductor memory device of claim 1 , wherein:
the coefficient selecting circuit includes a first selector and a second selector;
the first selector, when the generation of the random number sequence in the random number generator is started, selects, on the basis of the first value, one of the plurality of first coefficient groups for activating or deactivating the feedback loop, and outputs the selected one of the plurality of first coefficient groups to the second selector, the first value being generated from the group of bits of the address value of the data to be randomized by the random number sequence; and
the second selector, when the generation of the random number sequence in the random number generator is started, outputs the first coefficient input from the first selector to the random number generator, and when the generation of the random number sequence in the random number generator is continued, outputs the second coefficient to the random number generator.

9. A random number generating circuit comprising:
a random number generator including M (M is a positive integer) number of shift registers, having a feedback loop for a part of the M shift registers, and generating an M-bit random number sequence;
a coefficient selecting circuit that, when generation of the random number sequence in the random number generator is started, selects, on the basis of a first value, one of a plurality of first coefficient groups for activating or deactivating the feedback loop and outputs the selected one of the plurality of first coefficient groups as a first coefficient to the random number generator, and

Assignees

• Toshiba Kk

Inventors

• Kondo Yosuke

Classifications

• G06F7/584 Primary

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title