Integrated circuit, radar device and method of calibrating a receiver

US9835715B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9835715-B2
Application numberUS-201514660471-A
CountryUS
Kind codeB2
Filing dateMar 17, 2015
Priority dateOct 17, 2014
Publication dateDec 5, 2017
Grant dateDec 5, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

First claim

Opening claim text (preview).

The invention claimed is: 1. An integrated circuit for a radar device comprising at least one transmitter and at least one receiver, the integrated circuit comprising: a direct digital synthesiser, DDS, configured to output at least one control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS; wherein: in a first mode of operation the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver. 2. The integrated circuit of claim 1 wherein the DDS is configured to output a DC control signal in the first mode of operation and re-configured to output a low frequency control signal in the second mode of operation. 3. The integrated circuit of claim 2 wherein in the second mode of operation the at least one DDS control signal comprises two low frequency signals separated by 90 degrees. 4. The integrated circuit of claim 1 wherein the multiplier is at least one from a group of: a phase shifter, a radio frequency, RF, mixer, a RF quadrature mixer. 5. The integrated circuit of claim 1 wherein the multiplier is configured to realize vector modulation in the second mode of operation. 6. The integrated circuit of claim 1 wherein the multiplier cooperating with the DDS is configured to realize phase generation and low frequency generation in at least two modulated transmitter signals. 7. The integrated circuit of claim 1 wherein the local oscillator input signal comprises two radio frequency signals separated by 90 degrees. 8. A radar device comprising: at least one receiver to be calibrated; and at least one transmitter comprising: a direct digital synthesiser, DDS, configured to output at least one control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS; wherein: in a first mode of operation the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver. 9. The radar device of claim 8 wherein the DDS is configured to output a DC control signal in the first mode of operation and re-configured to output a low frequency control signal in the second mode of operation. 10. The radar device of claim 9 further comprising a signal processor configured to process the received at least two modulated transmitter signals; and calibrate the at least one receiver of the radar device using the processed at least at least one low frequency modulated transmitter signal. 11. The radar device of claim 10 further comprising a memory operably coupled to the signal processor and configured to store calibration information related to the at least one receiver of the radar. 12. The radar device of claim 8 further comprising a controller operably coupled to the DDS and adapted to re-configure the DDS to output at least one low frequency control signal in the second mode of operation. 13. The radar device of claim 8 wherein the radar device is from a group of: a long range radar device, short range radar device, operating at millimeter waveform frequencies. 14. A method of calibrating at least one receiver of a radar device, the method comprising: switching the radar device to a receiver calibration mode of operation; re-configuring a transmitter circuit of the radar device to generate at least one low frequency modulated transmitter signal; routing the generated at least one low frequency modulated transmitter signal to the at least one receiver internally within the radar device; processing the received at least one low frequency modulated transmitter signal; and calibrating the at least one receiver of the radar device using the processed at least one low frequency modulated transmitter signal. 15. The method of claim 14 wherein re-configuring a transmitter circuit of the radar device to generate at least one low frequency modulated transmitter signal comprises re-configuring a direct digital synthesiser to generate at least one digital intermediate frequency modulation signal. 16. The method of claim 15 wherein re-configuring the direct digital synthesiser to generate at least one digital intermediate frequency modulation signal comprises generating two digital intermediate frequency signals separated by 90 degrees. 17. The method of claim 14 wherein calibrating the at least one receiver comprises determining a phase difference between the at least two modulated transmitter signals routed through the at least one receiver path(s). 18. The method of claim 14 wherein the at least one low frequency modulated transmitter signal comprises at least two independently low frequency modulated signals. 19. The method of claim 14 wherein re-configuring a transmitter circuit of the radar device to generate at least one low frequency modulated transmitter signal comprises applying independent low frequency modulated control signals to two input local oscillator signals separated by 90 degrees.

Assignees

Inventors

Classifications

  • using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal · CPC title

  • G01S7/4056Primary

    specially adapted to FMCW · CPC title

  • Physics · mapped topic

  • of land vehicles · CPC title

  • involving an IF signal injection · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9835715B2 cover?
An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate…
Who is the assignee on this patent?
Delbecq Dominique, Doare Olivier, Montoriol Gilles, and 1 more
What technology area does this patent fall under?
Primary CPC classification G01S7/4056. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).