Multi-Chip Transceiver Testing in a Radar System
US-2017090015-A1 · Mar 30, 2017 · US
US2016146931A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016146931-A1 |
| Application number | US-201414550774-A |
| Country | US |
| Kind code | A1 |
| Filing date | Nov 21, 2014 |
| Priority date | Nov 21, 2014 |
| Publication date | May 26, 2016 |
| Grant date | — |
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Official abstract text for this publication.
A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
Opening claim text (preview).
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1 . A device comprising: a circuit board operable to receive electronic devices; a first radar chip disposed on said circuit board, said first radar chip comprising a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array, said first radar transmission antenna being operable to transmit a first radar transmission signal, said second radar transmission antenna being operable to transmit a second radar transmission signal; a second radar chip disposed on said circuit board, said second radar chip comprising a second radar receiver antenna array, said second radar chip being spaced from said first radar chip so as to create a virtual receiver antenna array between said first radar receiver antenna array and said second radar receiver antenna array; and a controlling component disposed on said circuit board, said controlling component being operable to control said first radar chip and said second radar chip. 2 . The device claim 1 , wherein said first radar receiver antenna array comprises a first radar receiver antenna, and wherein said first radar transmission antenna is spaced from said second radar transmission antenna so as to create a first virtual receiver antenna collocated with said first radar receiver antenna. 3 . The device of claim 2 , wherein said first radar receiver antenna is operable to generate a first radar received signal, wherein said first radar chip is operable to generate a first virtual received signal based on the second radar transmission signal and associated with said first virtual receiver antenna, and wherein said first radar chip is operable to perform a calibration procedure based on the first virtual received signal and the first radar received signal. 4 . The device claim 1 , wherein said second radar receiver antenna array comprises a second radar receiver antenna, and wherein said second radar chip is spaced from said first radar chip so as to create a second virtual receiver antenna collocated with said second radar receiver antenna. 5 . The device claim 4 , wherein said second radar receiver antenna is operable to generate a second radar received signal, wherein said first radar chip is further operable to generate a second virtual received signal based on the second radar transmission signal and associated with said second virtual receiver antenna, and wherein said controller component is still further operable to perform a calibration procedure based on the second virtual received signal and the second received radar signal. 6 . The device claim 1 , wherein said first radar chip includes a first side and a second side, wherein said first radar receiver antenna array is asymmetrically disposed so as to be closer to said first side than said second side, wherein said second radar chip includes a third side and a fourth side, wherein said second radar receiver antenna array is asymmetrically disposed so as to be closer to said third side than said fourth side, and wherein said first side is closer to said third side than said fourth side. 7 . The device of claim 1 , wherein said first radar chip further comprises a first ramp generator operable to generate a first frequency ramp signal, wherein said second radar chip further comprises a second ramp generator operable to generate a second frequency ramp signal, wherein each antenna in said first radar receiver antenna array comprises an associated mixer, respectively, wherein each antenna in said first radar receiver antenna array is operable to receive a respective receive signal, each respective receive signal corresponding to the first radar transmission signal, wherein each antenna in said first radar receiver antenna array is further operable to mix the respective receive signal with the first frequency ramp signal to generate a corresponding IF received signal, respectively, wherein said first radar chip is operable to generate a first combined IF received signal from a plurality of the IF received signals, wherein each antenna in said second radar receiver antenna array comprises an associated second array mixer, respectively, wherein each antenna in said second radar receiver antenna array is operable to receive a respective second array receive signal, each respective second array receive signal corresponding to the first radar transmission signal, wherein each antenna in said second radar receiver antenna array is further operable to mix the respective second array receive signal with the second frequency ramp signal to generate a corresponding second array IF received signal, respectively, and wherein said second radar chip is further operable to generate a second combined IF received signal from one of the second array IF received signals. 8 . The device of claim 7 , wherein said second ramp generator is operable to generate the second frequency ramp signal based on a signal received from a first local oscillator. 9 . The device claim 8 , wherein said controlling component further includes a comparing component operable to estimate a misalignment between said first radar chip and said second radar chip based on the first combined IF received signal and the second combined IF received signal, and wherein said comparing component includes a frequency analyzing component operable to generate a first frequency spectrum signal based on the first combined IF received signal, to generate a second frequency spectrum signal based on the second IF received signal, and to estimate a frequency offset between the first frequency spectrum signal and the second frequency spectrum signal. 10 . The device claim 7 , wherein said controlling component is further operable to provide a reference clock to said first radar chip and to said second radar chip, wherein said first ramp generator is operable to generate the first frequency ramp signal based on the reference clock, and wherein said second ramp generator is further operable to generate the second frequency ramp signal based on the reference clock. 11 . The device claim 10 , wherein said controlling component further comprises a comparing component operable to estimate a misalignment between said first radar chip and said second radar chip based on the IF received signal and the second array IF received signal, and wherein said comparing component comprises a frequency analyzing component operable to generate a first frequency spectrum signal based on the IF received signal, to generate a second frequency spectrum signal based on the second array IF received signal, and to estimate a frequency offset between the first frequency spectrum signal and the second frequency spectrum signal. 12 . A method comprising: controlling, via a controlling component disposed on a circuit board, a first radar chip disposed on the circuit board, the first radar chip comprising a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array; controlling, via the controlling component, a second radar chip disposed on the circuit board, the second radar chip comprising a second radar receiver antenna array; transmitting, via the first radar transmission antenna, a first radar transmission signal; transmitting, via the second radar transmission antenna, a second radar transmission signal, wherein the second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array
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