Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-9832883-B2
Application number	US-201313870644-A
Country	US
Kind code	B2
Filing date	Apr 25, 2013
Priority date	Apr 25, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package substrate comprising:
a first side that includes one or more lands, the one or more lands with a first surface finish disposed on the one or more lands;
a second side disposed opposite to the first side, the second side with an outer dielectric layer that has an outer surface, the outer surface being an outer surface of the package substrate; and
one or more electrical routing features disposed in, and extending through, the outer dielectric layer, wherein the one or more electrical routing features have an outer surface that is coplanar with the outer surface of the outer dielectric layer, wherein a second surface finish is disposed on, and in direct contact with, the outer surface of the one or more electrical routing features, wherein the one or more electrical routing features have a pitch to bond with die interconnect structures of one or more dies, wherein the second surface finish has a different chemical composition than the first surface finish, wherein a bump pitch of the electrical routing features is 50 micrometers, and wherein the electrical routing features include a pad size of 49 micrometers.

2. The package substrate of claim 1 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more electrical routing features.

3. The package substrate of claim 1 , wherein the second surface finish is imidazole or an imidazole derivative.

4. The package substrate of claim 1 , wherein the second surface finish is gold.

5. The package substrate of claim 1 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers, wherein the electrical routing features include pads with a spacing between the pads of 1 micrometer.

6. The package substrate of claim 1 , wherein the second surface finish is disposed on the first surface finish of the one or more lands of the first side.

7. The package substrate of claim 1 , wherein the one or more electrical routing features disposed on the second side include one or more vias.

8. The package substrate of claim 1 , wherein the first surface finish comprises nickel (Ni).

9. The package substrate of claim 8 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

Assignees

• Intel Corp

Inventors

• Zhang Qinglei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title