Methods and devices for providing increased routing flexibility in multi-layer printed circuit boards

Patent metadata

Field	Value
Publication number	US-9832865-B2
Application number	US-201615138309-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	Apr 26, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.

First claim

What is claimed is:

1. A circuit board comprising:
a stack of at least first and second circuit board layers, each circuit board layer comprising a layer of a first type of dielectric material and a layer of metal that may be patterned or unpatterned, a first circuit board layer of the stack of at least first and second circuit board layers comprising a patterned metal layer, one or more of the circuit board layers having one or more electrically-conductive vias formed therein that extend from the metal layer of the respective circuit board layer to the metal layer of an adjacent circuit board layer; and
a mezzanine redistribution structure disposed inside of the layer of the first type of dielectric material of the first circuit board layer, and wherein the mezzanine redistribution structure comprises a non-sacrificial layer of a second type of dielectric material and a mezzanine redistribution layer of metal, the mezzanine redistribution layer of metal forming electrical interconnections between different portions of the patterned metal layer of the first circuit board layer.

2. The circuit board of claim 1 , wherein the first type of dielectric material is a resin material.

3. The circuit board of claim 2 , wherein the resin material has glass fibers woven throughout the resin material.

4. The circuit board of claim 2 , wherein the resin material of all of the circuit board layers except for the first circuit board layer has glass fibers woven throughout the resin material, and wherein the resin material of the first circuit board layer is devoid of the glass fibers.

5. The circuit board of claim 1 , wherein at least one of the circuit board layers above the first circuit board layer has a patterned metal layer comprising radio frequency (RF) routes and wherein the patterned metal layer of the first circuit board layer comprises digital routes.

6. The circuit board of claim 5 , wherein one of the circuit board layers in between the first circuit board layer and the circuit board layer comprising the RF routes has a metal layer that forms an electrical isolation barrier between RF signals carried on the RF routes and digital signals carried on the digital routes.

7. The circuit board of claim 1 , wherein the dielectric material of the second type is a photo-imageable dielectric material laminate.

8. The circuit board of claim 1 , wherein the dielectric material of the first type is different from the dielectric material of the second type, and wherein the mezzanine redistribution structure further comprises:
at least first and second electrically-conductive vias formed in the non-sacrificial layer, the first and second electrically-conductive vias having first ends that are in contact with first and second electrically-conductive contacts, respectively, of the patterned metal layer of the first circuit board layer, and wherein the mezzanine redistribution layer of metal extends between second ends of the first and second electrically-conductive vias.

9. The circuit board of claim 8 , wherein the first type of dielectric material is a resin material.

10. The circuit board of claim 9 , wherein the resin material has glass fibers woven throughout the resin material.

11. The circuit board of claim 9 , wherein the resin material of all of the circuit board layers except for the first circuit board layer has glass fibers woven throughout the resin material, and wherein the resin material of the first circuit board layer is devoid of the glass fibers.

12. The circuit board of claim 8 , wherein the second type of dielectric material is a photo-imageable dielectric material.

13. The circuit board of claim 8 , wherein the second type of dielectric material is a wet-etchable dielectric material.

14. The circuit board of claim 8 , wherein the second type of dielectric material is a dielectric ink.

15. The circuit board of claim 8 , wherein at least one of the circuit board layers above the first circuit board layer has a patterned metal layer comprising radio frequency (RF) routes and wherein the patterned metal layer of the first circuit board layer comprises digital routes.

16. The circuit board of claim 15 , wherein one of the circuit board layers in between the first circuit board layer and the circuit board layer comprising the RF routes has a metal layer that forms an electrical isolation barrier between RF signals carried on the RF routes and digital signals carried on the digital routes.

17. The circuit board of claim 16 , further comprising at least a third electrically-conductive via having a first end that is in contact with the metal layer that forms the electrical isolation barrier and a second end that is in contact with the mezzanine redistribution layer of metal.

18. The circuit board of claim 16 , further comprising at least a third electrically-conductive via having a first end that is in contact with the metal layer of the circuit board layer that is below the first circuit board layer in the stack and having a second end that is in contact with an electrically-conductive contact of the patterned layer of metal of the first circuit board layer.

19. The circuit board of claim 8 , wherein the second type of dielectric material is a laminate.

20. The circuit board of claim 8 , wherein the mezzanine redistribution structure has a height that is less than or equal to about 40 micrometers, and wherein the layers of the first type of dielectric material have a uniform height that is greater than the height of the mezzanine redistribution structure.

Assignees

• Avago Technologies General Ip

Inventors

• Ajoian Jack
• Jain Padam

Classifications

• H05K3/10

  in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K1/144

  Stacked arrangements of planar printed circuit boards · CPC title

• H05K2201/09281

  Layout details of a single conductor · CPC title