Asymmetrical multilayer substrate, RF module, and method for manufacturing asymmetrical multilayer substrate

Patent metadata

Field	Value
Publication number	US-9204533-B2
Application number	US-201213664358-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Oct 31, 2011
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.

First claim

What is claimed is:

1. An asymmetrical multilayer substrate comprising:
a core layer in which a through-hole for passing through and connecting upper and lower portions thereof is formed;
a first pattern layer formed on one of upper and lower portions of the core layer, and including a first signal line pattern connected with the through-hole;
a second pattern layer formed on the other of the upper and lower portions of the core layer, and including a second metal plate providing a capacitance between itself and a pattern of an adjacent outer pattern layer and a second routing line pattern connected with the through-hole;
a first insulating layer formed on the second pattern layer so as to have a thinner thickness than a thickness of the core layer, and including a first via connected with the second routing line pattern; and
a third pattern layer formed on the first insulating layer, and including a third signal line pattern connected with the first via,
wherein an impedance transformation circuit including an impedance load on a transmission line and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer, and the impedance load includes impedances of the through-hole, the second routing line pattern, and the first via which are forming the transmission line, and the parasitic capacitance load includes the capacitance provided by the second metal plate.

2. The asymmetrical multilayer substrate according to claim 1 , wherein the first pattern layer further includes a first metal plate facing the second metal plate, the parasitic capacitance load is a parallel parasitic capacitance load of first and second capacitances formed between the second metal plate and each of the third signal line pattern and the first metal plate, the third pattern layer further includes a third metal plate providing a capacitance between itself and the second routing line pattern, and an impedance of each of the first signal line pattern and the second routing line pattern is smaller than an impedance of the third signal line pattern.

3. The asymmetrical multilayer substrate according to claim 2 , wherein the third signal line pattern forms a micro-strip line together with the second metal plate, and the third metal plate is formed to adjust an impedance of the second routing line pattern.

4. The asymmetrical multilayer substrate according to claim 2 , wherein a width of each of the second metal plate and the first metal plate is larger than a width of the third signal line pattern.

5. The asymmetrical multi layer substrate according to claim 1 , further comprising:
a predetermined build-up structure comprising N laminated layers on one of upper and lower portions of the core layer and comprising N−1 laminated layers on the other of the upper and lower portions of the core layer, with N being a natural number of 2 or more,
wherein the predetermined build-up structure including a (2N−2)-th insulating layer formed on a (2N−3)-th pattern layer so as to have a thinner thickness than the thickness of the core layer and including a (2N−2)-th via connected with a (2N−3)-th signal line pattern included in the (2N−3)-th pattern layer, a 2N-th pattern layer formed on the (2N−2)-th insulating layer and including a 2N-th routing line pattern connected with the (2N−2)-th via and a 2N-th metal plate providing a ground, a (2N−1)-th insulating layer formed on the 2N-th pattern layer so as to have a thinner thickness than the thickness of the core layer and including a (2N−1)-th via connected with the 2N-th routing line pattern, and a (2N+1)-th pattern layer formed on the (2N−1)-th insulating layer and including a (2N+1)-th signal line pattern connected with the (2N−1)-th via,
and wherein asymmetrical layers of 2N+1layers are formed by the first to the (2N+1)-th pattern layers.

6. The asymmetrical multilayer substrate according to claim 5 , wherein the impedance load on the transmission line is an impedance load by at least two vias including the first via, at least one routing line pattern including the second routing line pattern, at least one signal line pattern, and the through-hole which are formed on a routing line between signal line patterns forming input and output terminals of the signal transmission, and the parasitic capacitance load on the transmission line is a capacitance load by the capacitance provided by the second metal plate and capacitances provided by at least one metal plate providing the grounds between itself and the signal line patterns forming the input and output terminals of the signal transmission.

7. The asymmetrical multilayer substrate according to claim 1 , wherein the second metal plate forms a ground with respect to the third signal line pattern.

8. The asymmetrical multilayer substrate according to claim 7 , wherein the parasitic capacitance load is a parallel capacitance formed between the second metal plate and each of the third and first signal line patterns.

9. The asymmetrical multilayer substrate according to claim 1 , wherein the impedance of each of the first signal line pattern and the second routing line pattern which are formed on the upper and lower portions of the core layer is smaller than an impedance of the third signal line pattern formed on the first insulating layer.

10. The asymmetrical multilayer substrate according to claim 1 , wherein the first pattern layer further includes a first metal plate facing the second metal plate, and the parasitic capacitance load is a parallel parasitic capacitance load of first and second capacitances formed between the second metal plate and each of the third signal line pattern and the first metal plate.

11. The asymmetrical multilayer substrate according to claim 1 , wherein the asymmetrical multilayer substrate is used in a mobile device.

12. A method for manufacturing an asymmetrical multilayer substrate, the method comprising:
preparing a core layer in which a through-hole for passing through and connecting upper and lower portions thereof is formed;
forming, on one of upper and lower portions of the core layer, a first pattern layer including a first signal line pattern connected with the through-hole;
forming, on the other of the upper and lower portions of the core layer, a second pattern layer including a second metal plate providing a capacitance between itself and a pattern of an adjacent outer pattern layer and a second routing line pattern connected with the through-hole;
forming, on the second pattern layer, a first insulating layer having a thinner thickness than a thickness of the core layer; and
forming a first via passing through the first insulating layer to be connected with the second routing pattern, and forming a third pattern layer, on the first insulating layer, a third pattern layer including a third signal line pattern connected with the first via,
wherein an impedance transformation circuit including an impedance load on a transmission line and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer, and the impedance load includes impedances of the through-hole, the second routing line pattern, and the first via which are forming the transmission line, and the parasitic capacitance load includes the capacitance provided by the second metal plate.

13. The method according to claim 12 , further comprising:
a predetermined build-up structure comprising N laminated layers on one of u

Assignees

• Samsung Electro Mech

Inventors

• Christian Romero
• Park Seung Wook
• Kweon Young Do
• Park Mi Jin

Classifications

• H05K2201/09336

  Signal conductors in same plane as power plane · CPC title

• H05K3/4602

  characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title

• H05K1/0251 Primary

  related to vias or transitions between vias and transmission lines · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title