Performance indicator for phase locked loops

Patent metadata

Field	Value
Publication number	US-9832011-B1
Application number	US-201615198115-A
Country	US
Kind code	B1
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

First claim

What is claimed is:

1. Performance indicator circuitry adapted to characterize performance of a phase locked loop (PLL) comprising an oscillator, a high pass path, and a low pass path comprising loop filter circuitry, wherein the PLL is in a phase path of a phase modulator, the performance indicator circuitry comprising:
first input circuitry configured to input a signal from the loop filter circuitry;
parameter calculation circuitry configured to:
compute a value for a performance indicator based on the signal; and
control an aspect of operation of the PLL based on the value;

second input circuitry configured to input a frequency modulation signal, comprising:
a reference filter that inputs the frequency modulation signal and outputs a filtered frequency modulation signal; and
a multiplexer that selects one of the filtered frequency modulation signal or the frequency modulation signal and inputs the selected signal to the parameter calculation circuitry; and

wherein the parameter calculation circuitry is configured to calculate the value based on a correlation between the loop filter signal and the frequency modulation signal.

2. The performance indicator circuitry of claim 1 , wherein the parameter calculation circuitry is configured to store the value in a memory for use in calibrating the PLL.

3. The performance indicator circuitry of claim 1 , wherein the parameter calculation circuitry is configured to provide the value to alignment circuitry, wherein the alignment circuitry is configured to process the frequency modulation signal for two point modulation by the PLL.

4. Performance indicator circuitry adapted to characterize performance of a phase locked loop (PLL) comprising an oscillator, a high pass path, and a low pass path comprising loop filter circuitry, wherein the PLL is in a phase path of a phase modulator, wherein the loop filter circuitry comprises gain circuitry that outputs an amplified signal, a low pass filter that outputs a filtered signal, and integrator circuitry that outputs an integrated signal, the performance indicator circuitry comprising:
first input circuitry comprising a multiplexer that selects one of the amplified signal, the low pass signal, or the integrated signal; and
parameter calculation circuitry configured to:
compute a value for a performance indicator based on the selected signal; and
control an aspect of operation of the PLL based on the value.

5. Performance indicator circuitry adapted to characterize performance of a phase locked loop (PLL) comprising an oscillator, a high pass path, and a low pass path comprising loop filter circuitry, wherein the PLL is in a phase path of a phase modulator, the performance indicator circuitry comprising:
first input circuitry configured to input a signal from the loop filter circuitry;
parameter calculation circuitry configured to compute a value of a statistical characterization of the loop filter signal over time and control an aspect of operation of the PLL based on the value; and
trigger circuitry configured to detect a trigger signal, and in response, cause the parameter calculation unit to compute the statistical characterization over a predetermined time period.

6. A phase modulator configured to process a frequency modulation signal to generate a phase modulated radio frequency (RF) signal for recombination with an amplitude modulation signal to generate a phase and amplitude modulated RF signal, the phase modulator comprising:
alignment circuitry configured to process the frequency modulation signal to produce a low pass signal and a high pass signal;
a phase locked loop, comprising:
an oscillator configured to generate the phase modulated RF signal based on a control signal;
a loop filter comprising a series of circuitry, wherein each circuitry in the loop filter is configured to output a respective unique loop filter signal; and
summation circuitry configured to add the high pass signal to an output of the loop filter to generate the control signal; and

performance indicator circuitry comprising:
first input circuitry configured to input a selected loop filter signal;
parameter calculation circuitry configured to compute a value for a performance indicator based at least on the loop filter signal; and
second input circuitry configured to input the frequency modulation signal, comprising:
a reference filter that inputs the frequency modulation signal and outputs a filtered frequency modulation signal; and
a multiplexer that selects one of the filtered frequency modulation signal or the frequency modulation signal and inputs the selected signal to the parameter calculation circuitry, and

wherein the parameter calculation circuitry is configured to calculate the value based on a correlation between the loop filter signal and the frequency modulation signal.

7. The phase modulator of claim 6 , wherein the parameter calculation circuitry is configured to store the value in a memory for use in calibrating the PLL.

8. The phase modulator of claim 6 , wherein the parameter calculation circuitry is configured to provide the value to the alignment circuitry for use in processing the frequency modulation signal.

9. A phase modulator configured to process a frequency modulation signal to generate a phase modulated radio frequency (RF) signal for recombination with an amplitude modulation signal to generate a phase and amplitude modulated RF signal, the phase modulator comprising:
alignment circuitry configured to process the frequency modulation signal to produce a low pass signal and a high pass signal;
a phase locked loop, comprising:
an oscillator configured to generate the phase modulated RF signal based on a control signal;
a loop filter comprising gain circuitry that outputs an amplified signal, a low pass filter that outputs a filtered signal, and integrator circuitry that outputs an integrated signal; and
summation circuitry configured to add the high pass signal to the output of the loop filter to generate the control signal; and

performance indicator circuitry comprising:
input circuitry comprising a multiplexer that selects one of the amplified signal, the low pass signal, or the integrated signal; and
parameter calculation circuitry configured to compute a value for a performance indicator based at least on the selected signal.

10. A phase modulator configured to process a frequency modulation signal to generate a phase modulated radio frequency (RF) signal for recombination with an amplitude modulation signal to generate a phase and amplitude modulated RF signal, the phase modulator comprising:
alignment circuitry configured to process the frequency modulation signal to produce a low pass signal and a high pass signal;
a phase locked loop, comprising:
an oscillator configured to generate the phase modulated RF signal based on a control signal;
a loop filter comprising a series of circuitry, wherein each circuitry in the loop filter is configured to output a respective unique loop filter signal; and
summation circuitry configured to add the high pass signal to the output of the loop filter circuitry to generate the control signal; and

performance indicator circuitry comprising:
input circuitry configured to input a selected loop filter signal; and
parameter calculation circuitry configured to compute a statistical characterization of the loop filter signal over time; and
trigger circuitry configured to detect a trigger signal, and in response, cause the parameter calculation unit to compute the statistical characterization.

11. A method for use with a phase locked loop comprising an oscillator configured to generate a phase modulated signa

Assignees

• Intel Ip Corp

Inventors

• Wicpalek Christian
• Buckel Tobias
• Menkhoff Andreas

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03C3/0941

  applying frequency modulation at more than one point in the loop · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H04L41/0681

  Configuration of triggering conditions · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title