Staggered parity

Patent metadata

Field	Value
Publication number	US-9831987-B2
Application number	US-201615378834-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Dec 9, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Forward Error Correction technique: parity vectors are computed such that each parity vector spans multiple FEC frames; in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and the parity vectors are staggered with respect to any sequence in which the FEC frames are processed. Values of decoded bits of a first frame are deduced from known bits of a first parity vector having an effective length of one frame. For parity vectors having an effective length greater than one frame, a Log Likelihood Ratio of each unknown bit associated with the first frame is updated based on known and unknown bits of each parity vector. First frame is decoded using deduced bit values and updated LLR values.

First claim

What is claimed is:

1. A method of forward error correction (FEC), the method comprising a FEC encoder:
processing a data signal to generate a sequence of FEC frames; and
computing parity vectors such that
each parity vector spans multiple FEC frames;
in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and
the parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

2. The method as claimed in claim 1 , wherein at least one of the parity vectors is computed using a binary Single Parity Check (SPC) encoding scheme.

3. The method as claimed in claim 1 , wherein the bits of a parity vector are computed from a subset of rows or columns of rectangular product FEC frames.

4. The method as claimed in claim 3 , wherein the subset of rows or columns are dis-contiguous.

5. The method as claimed in claim 4 , wherein the subset of rows or columns associated with a first parity vector are interleaved with the subset of rows or columns associated with at least one other parity vector.

6. The method as claimed in claim 1 , wherein at least one of the parity vectors is computed using a Low Density Parity Check (LDPC) encoding scheme.

7. The method as claimed in claim 1 , further comprising a FEC decoder:
receiving a plurality of the FEC frames and parity vectors;
processing bits of a first parity vector and updating an estimate of at least one bit in a first FEC frame based on the processing result; and
decoding the first FEC frame using the updated estimate.

8. The method as claimed in claim 7 , wherein updating the estimate of at least one bit comprises computing a respective Log Likelihood Ratio (LLR) of the at least one bit.

9. The method as claimed in claim 7 , wherein processing bits of a first parity vector comprises:
deducing values of parity bits of the first parity vector corresponding to a subset of bits of a first FEC frame that has been successfully decoded; and
calculating a local Log Likelihood Ratio (LLR) of parity bits of the first parity vector corresponding to a subset of bits of a second FEC frame that has not been successfully decoded.

10. The method as claimed in claim 8 , wherein updating the estimate of at least one bit comprises computing the sum of an LLR of the at least one bit and the processing result.

11. A Forward Error Correction (FEC) encoder comprising:
a processor configured to process an input data signal to generate a sequence of FEC frames; and
a parity calculator configured to compute parity vectors such that
each parity vector spans multiple FEC frames,
in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and
the parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

12. The Forward Error Correction encoder as claimed in claim 11 , wherein at least one of the parity vectors is computed using a binary Single Parity Check (SPC) encoding scheme.

13. The Forward Error Correction encoder as claimed in claim 11 , wherein at least one of the parity vectors is computed using a Low Density Parity Check (LDPC) encoding scheme.

14. The Forward Error Correction encoder as claimed in claim 11 , wherein the bits of a parity vector are computed from a subset of rows or columns of rectangular product FEC frames.

15. The Forward Error Correction encoder as claimed in claim 14 , wherein the subset of rows or columns are dis-contiguous.

16. The Forward Error Correction encoder as claimed in claim 15 , wherein the subset of rows or columns associated with a first parity vector are interleaved with the subset of rows or columns associated with at least one other parity vector.

17. A Forward Error Correction (FEC) decoder comprising:
a buffer configured to receive a plurality of FEC frames; and
a processor configured to
process bits of a first parity vector and update an estimate of at least one bit in a first FEC frame based on the processing result; and
decode the first FEC frame using the updated estimate,

wherein the processor is configured to update an estimate of at least one bit in a first FEC frame by
deducing a value of decoded data bits of a first FEC frame associated with a first parity vector having an effective length of one FEC frame, based on known values of parity bits of the first parity vector; and
for each parity vector having an effective length corresponding to more than one FEC frame, updating a Log Likelihood Ratio (LLR) of each unknown parity bit associated with the first FEC frame based on known and unknown parity bit values of each parity vector,
wherein the effective length of any parity vector is the number of FEC frames associated with unknown bits in that parity vector.

18. A Forward Error Correction (FEC) decoder comprising:
a buffer configured to receive a plurality of FEC frames; and
a processor configured to
process bits of a first parity vector and update an estimate of at least one bit in a first FEC frame based on the processing result; and
decode the first FEC frame using the updated estimate,

wherein the plurality of FEC frames and the first parity vector were generated by a Forward Error Correction encoder comprising
a processor configured to process an input data signal to generate a sequence of FEC frames; and
a parity calculator configured to compute parity vectors such that
each parity vector spans multiple FEC frames,
in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and
the parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

Assignees

• Oveis Gharan Shahab
• Harley James
• Roberts Kim B
• Ciena Corp

Inventors

• Oveis Gharan Shahab
• Harley James
• Roberts Kim B

Classifications

• H03M13/2921

  wherein error correction coding involves a diagonal direction · CPC title

• H03M13/2945

  using at least three error correction codes (H03M13/2957 takes precedence) · CPC title

• H03M13/2918

  with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube · CPC title

• H03M13/2963

  Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes · CPC title

• H03M13/2915

  with an error detection code in one dimension · CPC title