Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9831316-B2
Application number	US-201515303730-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Jul 11, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a wide gap semiconductor substrate;
an element portion formed on the wide gap semiconductor substrate, the element portion comprising: a low resistance semiconductor layer of a first conductive type; a drift layer of a first conductive type having a lower density of impurity than the low resistance semiconductor layer; a body layer of a second conductive type opposite to the first conductive type, the body layer positioned over the drift layer; a gate trench formed so as to open in the body layer and to reach the drift layer; a source region of the first conductive type formed in a state where the source region is arranged in the inside of the body layer and at least a portion of the source region is exposed on an inner peripheral surface of the gate trench; a gate insulation layer formed on the inner peripheral surface of the gate trench; a gate electrode layer formed inside the gate trench by way of the gate insulation layer; and a source electrode layer formed in a state where the source electrode layer is insulated from the gate electrode layer and is brought into contact with the source region; and
a gate pad portion formed on the wide gap semiconductor substrate, the gate pad portion comprising: a low resistance semiconductor layer of a first conductive type; a drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer; a second-conductive-type semiconductor layer of the second conductive type positioned on the drift layer; an insulation layer formed on the second-conductive-type semiconductor layer; and a gate line formed on the insulation layer, wherein
the element portion further includes a first trench structure which has: a plurality of first protective trenches where the first protective trenches open in the body layer in a region between the gate trenches formed adjacently to each other and are formed deeper than the gate trenches and shallower than the low resistance semiconductor layer; and a first buried layer formed inside the respective first protective trenches, and
the gate pad portion further includes a second trench structure which has: a plurality of second protective trenches where the second protective trenches open in the second-conductive-type semiconductor layer and are formed deeper than the gate trenches and shallower than the low resistance semiconductor layer; and a second buried layer formed inside the respective second protective trenches,
the first trench structure is either one of a structure where the first trench structure further includes a first semiconductor region of the second conductive type formed on at least a bottom portion of the first protective trench and a first buried layer which is made of a conductor as the first buried layer, and the first buried layer is connected with the drift layer through the first semiconductor region or a structure where the first trench structure includes a first buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the first protective trench as the first buried layer and the first buried layer forms the drift layer and the Schottky contact,
the second trench structure is either one of a structure where the second trench structure further includes a second semiconductor region of the second conductive type formed on at least a bottom portion of the second protective trench and a second buried layer which is made of a conductor as the second buried layer, and the second buried layer is connected with the drift layer through the second semiconductor region or a structure where the second trench structure includes a second buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the second protective trench as the second buried layer and the second buried layer forms the drift layer and the Schottky contact, and
the first buried layer and the second buried layer are electrically connected with the source electrode layer.

2. The semiconductor device according to claim 1 , wherein a depth of the second protective trench is equal to a depth of the first protective trench.

3. The semiconductor device according to claim 1 , wherein a width of an opening formed in the second protective trench is equal to a width of an opening formed in the first protective trench.

4. The semiconductor device according to claim 1 , wherein the second protective trench extends to a region where the element portion is formed as viewed in a plan view.

5. The semiconductor device according to claim 4 , wherein the second protective trench is formed in a state where the second protective trench is continuously formed with the first protective trench.

6. The semiconductor device according to claim 1 , wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and
the second trench structure further includes: a second side wall insulation layer formed on a side portion of the second protective trench; and a second semiconductor region formed on a bottom portion of the second protective trench as the second semiconductor region.

7. The semiconductor device according to claim 1 , wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and
the second trench structure further includes: a second side wall insulation layer formed on a side portion of the second protective trench; and a second semiconductor region formed in a position surrounding the second buried layer and the second side wall insulation layer on a bottom portion and a side portion of the second protective trench as the second semiconductor region.

8. The semiconductor device according to claim 1 , wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and
the second trench structure includes a second semiconductor region formed on a bottom portion and a side portion of the second protective trench as the second semiconductor region.

9. The semiconductor device according to claim 1 , wherein the element portion further has a third trench structure which has the same structure as the first trench structure on a more gate pad portion side than a gate trench closest to the gate pad portion among the plurality of gate trenches.

10. A method of manufacturing a semiconductor device for manufacturing the semiconductor device according to claim 1 , the method comprising:
a wide gap semiconductor substrate preparing step of preparing the wide gap semiconductor substrate on which the element portion which includes: the low resistance semiconductor layer of a first conductive type; the drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer; the body layer of the second conductive type opposite to the first conductive type, the body layer positioned over the drift layer; and the source region of the first conductive type formed in the inside of the body layer; and the gate pad portion which includes: the low resistance semiconductor layer of a first conductive type; the drift

Assignees

• Shindengen Electric Mfg

Inventors

• Inoue Tetsuto
• Sugai Akihiko
• Nakamura Shunichi

Classifications

• H01L29/12

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/06

  Electricity · mapped topic

• H01L29/407 Primary

  Electricity · mapped topic

• H01L29/408

  Electricity · mapped topic