Three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-9831267-B2
Application number	US-201615239434-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	Sep 22, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor device comprising:
a plurality of stack structures extending in one direction on a substrate, the stack structures spaced apart from each other, and each of the stack structures having a sidewall defining recess regions vertically spaced apart from each other;
a plurality of vertical structures penetrating the stack structures;
a common source plug between the stack structures that are adjacent to each other, the common source plug extending in parallel to the stack structures; and
a spacer structure at each side of the common source plug between the common source plug and the stack structures, the spacer structure covering the sidewalls of the stack structures,
the spacer structure including an insulating spacer and a protection spacer,
the insulating spacer filling the recess regions of the sidewalls of the stack structures,
a surface of the insulating spacer defining grooves,
the protection spacer filling the grooves of the surface of the insulating spacer, and

the protection spacer having a substantially flat surface.

2. The 3D semiconductor device of claim 1 , wherein the substantially flat surface of the protection spacer is in contact with the common source plug.

3. The 3D semiconductor device of claim 1 , wherein the common source plug includes:
a metal layer between the stack structures that are adjacent to each other; and
a barrier metal layer conformally covering a bottom surface and sidewalls of the metal layer, and
the barrier metal layer is in contact with the substantially flat surface of the protection spacer.

4. The 3D semiconductor device of claim 1 , wherein each of the stack structures includes:
insulating layers and electrodes alternately and vertically stacked on the substrate, wherein
sidewalls of the electrodes are laterally recessed from sidewalls of the insulating layers to define the recess regions,
the insulating spacer includes first portions adjacent to the electrodes and second portions adjacent to the insulating layers, and
a horizontal distance between a surface of the first portions and a surface of the second portions is smaller than a horizontal distance between the sidewall of the insulating layer adjacent to the insulating spacer and the sidewall of the electrode adjacent to the insulating spacer.

5. The 3D semiconductor device of claim 1 , wherein
the insulating spacer is formed of silicon oxide, and
the protection spacer is formed of one of silicon, germanium, and silicon-germanium.

6. The 3D semiconductor device of claim 1 , wherein the protection spacer includes:
a first protection spacer filling the grooves of the insulating spacer; and
a second protection spacer between the first protection spacer and the common source plug and having the substantially flat surface.

7. The 3D semiconductor device of claim 6 , wherein
the first protection spacer is formed of silicon, and
the second protection spacer is formed of silicon oxide.

8. The 3D semiconductor device of claim 1 , further comprising:
a data storage layer between the vertical structures and the stack structures, wherein
each of the stack structures includes insulating layers and electrodes alternately and vertically stacked on the substrate,
the data storage layer includes a vertical insulating pattern and horizontal pattern,
the vertical insulating pattern penetrates the stack structures to surround the vertical structures, and
the horizontal insulating pattern laterally extends between the vertical insulating pattern and each of the electrodes into between the each of the electrodes and the insulating layers.

9. The 3D semiconductor device of claim 8 , wherein the horizontal insulating patterns further extends into between the spacer structure and the insulating layers.

10. The 3D semiconductor device of claim 1 , further comprising:
a common source region formed in the substrate between the stack structures adjacent to each other,
wherein the common source plug is in contact with the common source region.

11. A three-dimensional (3D) semiconductor device comprising:
a plurality of stack structures extending in one direction on a substrate, the stack structures spaced apart from each other, and each of the stack structures having a sidewall defining recess regions vertically spaced apart from each other;
a plurality of vertical structures penetrating the stack structures;
a common source plug between the stack structures adjacent to each other, the common source plug extending in parallel to the stack structures; and
a spacer structure between the common source plug and the stack structures, the spacer structure at each side of the common source plug, the spacer structure covering the sidewalls of the stack structures,
the spacer structure including an insulating spacer and a protection spacer,
the insulating spacer filling the recess regions of the sidewalls of the stack structures,

a surface of the insulating spacer defining grooves,
the protection spacer filling the grooves of the insulating spacer,
the protection spacer being in contact with the common source plug, and the protection spacer includes a different material from the insulating spacer.

12. The 3D semiconductor device of claim 11 , wherein a surface of the protection spacer that contacts the common source plug is substantially flat.

13. The 3D semiconductor device of claim 11 , wherein the protection spacer includes:
a first protection spacer filling the grooves of the insulating spacer; and
a second protection spacer between the first protection spacer and the common source plug and having a substantially flat surface, and
the first protection spacer and the second protection spacer are formed of different materials.

14. The 3D semiconductor device of claim 11 , further comprising:
a data storage layer between the vertical structures and the stack structures, wherein
each of the stack structures includes insulating layers and electrodes alternately and vertically stacked on the substrate,
the data storage layer includes a vertical insulating pattern and horizontal pattern,
the vertical insulating pattern penetrates the stack structure to surround the vertical structures, and
the horizontal insulating pattern laterally extends between the vertical insulating pattern and each of the electrodes into between the each of the electrodes and the insulating layers.

15. The 3D semiconductor device of claim 11 , wherein
each of the stack structures includes insulating layers and electrodes alternately and vertically stacked on the substrate,
sidewalls of the electrodes are laterally recessed from sidewalls of the insulating layers to define the recess regions,
the insulating spacer includes first portions and second portions,
the first portions are adjacent to the electrodes,
the second portions are adjacent to the insulating layers, and
a horizontal distance between a surface of the first portions and a surface of the second portions is smaller than a horizontal distance between the sidewall of the insulating layer adjacent to the insulating spacer and the sidewall of the electrode adjacent to the insulating spacer.

16. A three-dimensional (3D) semiconductor device comprising:
a plurality of cell strings on a substrate, each of the cell strings including a plurality of memory cells stacked on top of each other between a ground selection transistor and a string selection transistor;
word lines connected to memory cells in the plurality of cell strings;
bit lines connected to the cell string

Assignees

• Kim Seulye
• Choi Ji-Hoon
• Kim Dongkyum
• Kim Jung Ho
• Noh Jintae
• Lee Eun-Young
• Samsung Electronics Co Ltd

Inventors

• Kim Seulye
• Choi Ji-Hoon
• Kim Dongkyum
• Kim Jung Ho
• Noh Jintae
• Lee Eun-Young

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L21/76843

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic

• H01L21/76816

  Electricity · mapped topic