Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9082653-B2
Application number	US-201414561788-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Jul 12, 2012
Publication date	Jul 14, 2015
Grant date	Jul 14, 2015

Abstract

A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower insulating pattern disposed on a substrate;
a lower gate pattern disposed on the lower insulating pattern;
a residual insulating pattern disposed on the lower gate pattern;
a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
a diffusion barrier pattern disposed on an upper surface of the first upper gate pattern and a side surface of the first upper gate pattern, wherein the side surface of the first upper gate pattern is adjacent to the opening; and
a second upper gate pattern disposed on the diffusion barrier pattern and filling the opening, wherein an upper surface of the second upper gate pattern in the opening is below an upper surface of the diffusion barrier pattern disposed on the upper surface of the first upper gate pattern.

2. The semiconductor device of claim 1 , wherein the diffusion barrier pattern directly contacts the first upper gate pattern.

3. The semiconductor device of claim 1 , wherein the diffusion barrier pattern directly contacts the second upper gate pattern.

4. The semiconductor device of claim 1 , wherein the diffusion barrier pattern has an L-shape on the upper surface of the first upper gate pattern and the side surface of the first upper gate pattern.

5. The semiconductor device of claim 1 , wherein the diffusion barrier pattern includes silicon oxide, silicon oxynitride, or silicon nitride.

6. The semiconductor device of claim 1 , wherein the residual insulating pattern directly contacts the first upper gate pattern.

7. The semiconductor device of claim 1 , wherein the first and second upper gate patterns include polysilicon.

8. The semiconductor device of claim 1 , further comprising a metal barrier pattern disposed on the second upper gate pattern in the opening, wherein an upper surface of the metal barrier pattern in the opening is below the upper surface of the first upper gate pattern.

9. A NAND flash memory device comprising:
a lower insulating pattern disposed on a substrate;
a lower gate pattern disposed on the lower insulating pattern;
a residual insulating pattern disposed on the lower gate pattern;
a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
a diffusion barrier pattern disposed on an upper surface of the first upper gate pattern and a side surface of the first upper gate pattern, wherein the side surface of the first upper gate pattern is adjacent to the opening; and
a second upper gate pattern disposed on the diffusion barrier pattern and filling the opening, wherein the second upper gate pattern does not completely fill the opening.

10. The memory device of claim 9 , wherein the diffusion barrier pattern directly contacts the first upper gate pattern.

11. The memory device of claim 9 , wherein the diffusion barrier pattern directly contacts the second upper gate pattern.

12. The memory device of claim 9 , wherein the diffusion barrier pattern has an L-shape on the upper surface of the first upper gate pattern and the side surface of the first upper gate pattern.

13. The memory device of claim 9 , wherein the diffusion harrier pattern includes silicon oxide, silicon oxynitride, or silicon nitride.

14. The memory device of claim 9 , wherein the first and second upper gate patterns include polysilicon.

15. A semiconductor device, comprising:
a lower insulating pattern disposed on a substrate;
a lower gate pattern disposed on the lower insulating pattern;
a residual insulating pattern disposed on the lower gate pattern;
a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
a diffusion barrier pattern disposed on an upper surface of the first upper gate pattern and a side surface of the first upper gate pattern, wherein the diffusion barrier pattern disposed on the side surface of the first upper gate pattern forms a portion of a sidewall of the opening;
a second upper gate pattern disposed on the diffusion barrier pattern and filling the opening; and
a metal barrier pattern disposed on the second upper gate pattern in the opening.

16. The semiconductor device of claim 15 , further comprising a peripheral transistor, wherein the peripheral transistor includes:
a lower insulating pattern disposed on the substrate;
a lower gate pattern disposed on the lower insulating pattern;
a residual insulating pattern disposed on the lower gate pattern;
a first upper gate pattern disposed on the residual insulating pattern;
a diffusion barrier pattern disposed on the first upper gate pattern; and
a second upper gate pattern disposed on the diffusion barrier pattern.

17. The semiconductor device of claim 16 , wherein the diffusion barrier pattern of the peripheral transistor has a non-planar shape.

18. The semiconductor device of claim 15 , wherein the diffusion barrier pattern is in direct contact with the upper surface of the first upper gate pattern and the side surface of the first upper gate pattern.

19. The semiconductor device of claim 15 , wherein the diffusion barrier pattern. includes silicon oxide, silicon oxynitride, or silicon nitride.

20. The semiconductor device of claim 15 , wherein the first and second upper gate patterns include polysilicon.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Hauk
• Kwon Yong-Il
• Oh Jungsuk
• Ryu Tae Sun
• Lee Jeonggil

Classifications

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10D30/681 Primary

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D64/664

  the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title