Semiconductor device

Patent metadata

Field	Value
Publication number	US-9099447-B2
Application number	US-201213659229-A
Country	US
Kind code	B2
Filing date	Oct 24, 2012
Priority date	Oct 26, 2010
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first impurity diffusion region formed in a substrate;
an isolation region formed in the substrate, the isolation region surrounding the first impurity diffusion region or separating the first impurity diffusion region from another impurity diffusion region;
a potential supply interconnect formed in an interconnect layer above the first impurity diffusion region, and extending in a first direction;
a first local interconnect formed in contact with an upper surface of the first impurity diffusion region and an upper surface of the isolation region, and disposed below the potential supply interconnect; and
a first contact hole electrically coupling the first local interconnect to the potential supply interconnect.

2. The semiconductor device of claim 1 , further comprising:
a second impurity diffusion region formed in the substrate;
a second local interconnect formed in contact with an upper surface of the second impurity diffusion region, and disposed below the potential supply interconnect; and
a second contact hole electrically coupling the second local interconnect to the potential supply interconnect.

3. The semiconductor device of claim 2 , wherein
the first and second contact hole are aligned in a straight line along the potential supply interconnect.

4. The semiconductor device of claim 2 , wherein
the first and second local interconnects are integrally formed, and
the first and second contact holes are used in common and integrally formed.

5. The semiconductor device of claim 2 , wherein
the second local interconnect is formed in contact with the upper surface of the isolation region.

6. The semiconductor device of claim 1 , further comprising:
a reinforcing impurity diffusion region formed in the substrate below the potential supply interconnect; and
a reinforcing local interconnect formed in contact with an upper surface of the reinforcing impurity diffusion region, extending in the first direction, and electrically coupled to the potential supply interconnect via a contact hole, wherein
the reinforcing local interconnect is integrally formed with the first local interconnect.

7. The semiconductor device of claim 1 , further comprising
a reinforcing impurity diffusion region formed in the substrate below the potential supply interconnect, extending in the first direction, and electrically coupled to the potential supply interconnect via a contact hole,
wherein the first local interconnect is formed in contact with an upper surface of the reinforcing impurity diffusion region.

8. The semiconductor device of claim 1 , further comprising
a second impurity diffusion region formed in the substrate, and being adjacent to the first impurity diffusion region with the potential supply interconnect interposed therebetween in a second direction orthogonal to the first direction, wherein
the first local interconnect extends from a portion below the potential supply interconnect to an upper surface of the second impurity diffusion region, and formed in contact with the upper surface of the second impurity diffusion region.

9. The semiconductor device of claim 1 , further comprising
a vacant space being adjacent to the first impurity diffusion region with the potential supply interconnect interposed therebetween in a second direction orthogonal to the first direction, wherein
the first local interconnect extends from a portion below the potential supply interconnect to the vacant space so that the first local interconnect and the potential supply interconnect form a cross shape in a plan view.

10. The semiconductor device of claim 1 , further comprising
a second impurity diffusion region formed in the substrate, and being adjacent to the first impurity diffusion region in the first direction, wherein
the first local interconnect extends from the upper surface of the first impurity diffusion region to an upper surface of the second impurity diffusion region, and is formed in contact with the second impurity diffusion region.

11. The semiconductor device of claim 1 , further comprising:
a gate electrode;
an interconnect formed in the interconnect layer;
a second local interconnect formed in contact with the gate electrode; and
a second contact hole electrically coupling the second local interconnect to the interconnect.

12. The semiconductor device of claim 1 , wherein
an entirety of the first contact hole is disposed over the isolation region.

13. The semiconductor device of claim 1 , wherein
the first local interconnect extends in a second direction orthogonal to the first direction from a portion below the potential supply interconnect to the upper surface of the first impurity diffusion region across the isolation region.

14. The semiconductor device of claim 1 , further comprising:
a gate electrode extending in a second direction orthogonal to the first direction,
wherein the first local interconnect extends in the second direction from a portion below the potential supply interconnect to the upper surface of the first impurity diffusion region across the isolation region.

15. A semiconductor device comprising:
a first impurity diffusion region formed in a substrate;
an isolation region formed in the substrate, the isolation region surrounding the first impurity diffusion region or separating the first impurity diffusion region from another impurity diffusion region;
a gate electrode formed over the first impurity diffusion region and the isolation region;
an interconnect formed in an interconnect layer, the interconnect layer being located above a layer in which the gate electrode is formed;
a local interconnect formed in contact with the gate electrode and an upper surface of the isolation region; and
a contact hole electrically coupling the local interconnect to the interconnect and disposed over the isolation region.

Assignees

• Panasonic Corp
• Socionext Inc

Inventors

• Tamaru Masaki

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/966

  Gate electrode terminals or contacts · CPC title

• H10D84/961

  Substrate and well contacts · CPC title