Method of fabricating package substrates

Patent metadata

Field	Value
Publication number	US-9831217-B2
Application number	US-201715465775-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Apr 15, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.

First claim

What is claimed is:

1. A method for fabricating a package substrate, comprising steps of:
(A) providing a first carrier substrate;
(B) forming a first conductive wire and a first connecting unit on the first carrier substrate;
(C) forming a first dielectric layer on the first carrier substrate while enabling the first conductive wire and the first connecting unit to be surrounded by the first dielectric layer and an end face of the first connecting unit to be exposed;
(D) bonding a second carrier substrate to the first dielectric layer and then removing the first carrier substrate;
(E) disposing a first circuit chip and a second connecting unit on the first conductive wire;
(F) forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed;
(G) forming a second conductive wire on the second dielectric layer;
(H) disposing a second circuit chip on the second conductive wire;
(I) forming a third dielectric layer on the second carrier substrate; and
(J) removing the second carrier substrate.

2. The method of claim 1 , wherein the step (B) includes:
(B11) forming the first conductive wire on the first carrier substrate; and
(B12) forming the first connecting unit on the first conductive wire.

3. The method of claim 1 , wherein the step (C) includes:
(C11) forming the first dielectric layer on the first carrier substrate while enabling the first conductive wire and the first connecting unit to be covered by the first dielectric layer; and
(C12) partly removing the first dielectric layer to expose the end face of the first connecting unit.

4. The method of claim 1 , wherein the first circuit chip is disposed before the second connecting unit in the step (E).

5. The method of claim 1 , wherein the second connecting unit is disposed before the first circuit chip in the step (E).

6. The method of claim 1 , wherein the first circuit chip and the second connecting unit are not vertically overlapped in the step (E).

7. The method of claim 1 , wherein the second connecting unit is formed by electrolytic plating.

8. The method of claim 1 , wherein the second connecting unit includes a metal pillar.

9. The method of claim 1 , wherein the step (F) includes:
(F11) forming the second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be covered by the second dielectric layer; and
(F12) partly removing the second dielectric layer to expose the end face of the second connecting unit.

10. The method of claim 1 , wherein the second conductive wire is formed on the second dielectric layer while enabling the second conductive wire to be in contact with the exposed end face of the second connecting unit in the step (G).

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hu Chu-Chin
• Hsu Shih-Ping
• Hsu Che-Wei
• Liu Chin-Ming
• Yang Chih-Kuai

Classifications

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/295

  optical coupling · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title