Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US9831165B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9831165-B2 |
| Application number | US-201414547743-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 19, 2014 |
| Priority date | Aug 29, 2014 |
| Publication date | Nov 28, 2017 |
| Grant date | Nov 28, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.
Opening claim text (preview).
What is claimed is: 1. An interposer substrate, comprising: a first insulating layer having a first surface and a second surface opposing to the first surface; a first wiring layer formed on the first surface of the first insulating layer wherein the first wiring layer has a surface lower than the first surface of the first insulating layer; a plurality of conductive pillars formed in the first insulating layer and on the first wiring layer, and connected to the second surface of the first insulating layer; a second wiring layer formed on the second surface of the first insulating layer and electrically connected with the conductive pillars; and a second insulating layer formed on the second surface of the first insulating layer and the second wiring layer, wherein a portion of a surface of the second wiring layer is exposed from the second insulating layer, and the surface of the second wiring layer is flush with or lower than a surface of the second insulating layer and free from being in contact with the second surface of the first insulating layer. 2. The interposer substrate of claim 1 , wherein the first insulating layer is made of a molding compound, a primer, or a dielectric material. 3. The interposer substrate of claim 1 , wherein the conductive pillars have a terminal surface flush with the second surface of the first insulating layer. 4. The interposer substrate of claim 1 , wherein the second wiring layer is a plurality of solder ball pads. 5. The interposer substrate of claim 1 , wherein the second insulating layer is made of a molding compound, a primer, or a dielectric material. 6. The interposer substrate of claim 1 , further comprising a supporting structure disposed on the first surface of the first insulating layer.
Organic materials · CPC title
Shapes or dispositions thereof · CPC title
of vias therein · CPC title
Through-vias · CPC title
Temporary metallic carrier, e.g. for transferring material · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.