Integrated fan-out package including voltage regulators and methods forming same

Patent metadata

Field	Value
Publication number	US-9831148-B2
Application number	US-201615169857-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Mar 11, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.

First claim

What is claimed is:

1. A method comprising:
adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die;
encapsulating the voltage regulator die in an encapsulating material;
planarizing the encapsulating material, wherein a back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die;
forming first dielectric layers over the voltage regulator die and the encapsulating material;
forming first redistribution lines in the first dielectric layers, wherein portions of the first redistribution lines are electrically coupled to the through-via;
replacing the die-attach film with a dielectric material;
forming second dielectric layers, wherein the first and the second dielectric layers are on opposite sides of the voltage regulator die;
forming second redistribution lines in the second dielectric layers; and
bonding an additional device die to the second redistribution lines, with the voltage regulator die electrically coupled to the additional device die, and the through-via is electrically disconnected from all circuits in the voltage regulator die.

2. The method of claim 1 further comprising forming a conductive post over the carrier, wherein the conductive post is encapsulated by the encapsulating material, and the conductive post electrically inter-couples the first redistribution lines to the second redistribution lines.

3. The method of claim 1 , wherein the voltage regulator die further comprises metal pillars embedded in the die-attach film, with surfaces of the metal pillars and a surface of the die-attach film being coplanar and in contact with a base layer over the carrier, wherein the replacing the die-attach film comprises:
etching the die-attach film to form a recess in the encapsulating material;
filling the dielectric material into the recess; and
performing an additional planarization to remove excess portions of the dielectric material, until the metal pillars in the voltage regulator die are exposed.

4. The method of claim 1 further comprising encapsulating the additional device die in an additional encapsulating material.

5. The method of claim 1 , wherein when the voltage regulator die is adhered to the carrier, the die-attach film encircles metal pillars of the voltage regulator die, and surfaces of the metal pillars are coplanar with a surface of the die-attach film facing the carrier.

6. The method of claim 1 , wherein the replacing the die-attach film with the dielectric material comprises:
etching the die-attach film to form a recess in the encapsulating material;
forming metal pillars from metal pads in the voltage regulator die;
filling the dielectric material into the recess; and
performing an additional planarization to remove excess portions of the dielectric material, until the metal pillars are exposed.

7. A method comprising:
forming a base layer over a carrier;
forming a conductive post over the base layer;
adhering a voltage regulator die to the base layer, wherein the voltage regulator die comprises a die-attach film and metal pillars in the die-attach film, and a surface of the die-attach film and surfaces of the metal pillars are coplanar, and are adhered to, and in physical contact with, the base layer;
encapsulating the voltage regulator die and the conductive post in an encapsulating material;
planarizing the encapsulating material, until the voltage regulator die and the conductive post are exposed;
forming first dielectric layers over the voltage regulator die and the encapsulating material;
forming first redistribution lines in the first dielectric layers, wherein portions of the first redistribution lines are electrically coupled to the conductive post;
replacing the die-attach film with a dielectric material;
forming second dielectric layers, wherein the first and the second dielectric layers are on opposite sides of the voltage regulator die;
forming second redistribution lines in the second dielectric layers; and
bonding an additional device die to the second redistribution lines.

8. The method of claim 7 , wherein when the encapsulating material is planarized, a back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die, and wherein the through-via electrically couples the first redistribution lines to the second redistribution lines.

9. The method of claim 8 , wherein the through-via is electrically disconnected from all active circuits in the voltage regulator die.

10. The method of claim 7 , wherein the replacing the die-attach film comprises:
etching the die-attach film to form a recess in the encapsulating material;
filling the dielectric material into the recess; and
performing an additional planarization to remove excess portions of the dielectric material, until metal pillars in the voltage regulator die are exposed.

11. The method of claim 7 , wherein when the voltage regulator die is adhered to the base layer, the die-attach film encircles metal pillars of the voltage regulator die, and surfaces of the metal pillars are in contact with the base layer.

12. The method of claim 7 , wherein the replacing the die-attach film with the dielectric material comprises:
etching the die-attach film to form a recess in the encapsulating material;
forming metal pillars from metal pads in the voltage regulator die;
filling the dielectric material into the recess; and
performing an additional planarization to remove excess portions of the dielectric material, until the metal pillars are exposed.

13. The method of claim 7 further comprising encapsulating the additional device die in an additional encapsulating material.

14. A package comprising:
a voltage-regulator die comprising:
a semiconductor substrate;
a through-via penetrating through the semiconductor substrate; and
a metal pillar at a top surface of the voltage-regulator die, wherein the through-via is electrically disconnected from all active circuits in the voltage-regulator die;

a first encapsulating material encapsulating the voltage-regulator die therein;
a first plurality of redistribution lines over the voltage-regulator die and the first encapsulating material, wherein portions of the first plurality of redistribution lines comprises first portions electrically coupling to the through-via and second portions in physical contact with the metal pillar;
a device die bonded to the first plurality of redistribution lines; and
a second plurality of redistribution lines underlying the first encapsulating material, wherein the second plurality of redistribution lines is electrically coupled to the first plurality of redistribution lines.

15. The package of claim 14 further comprising a conductive post penetrating through the first encapsulating material.

16. The package of claim 15 , wherein a surface of the through-via, a surface of the conductive post, and a surface of the first encapsulating material are coplanar with each other.

17. The package of claim 14 , wherein the device die comprises a System-On-Chip die.

18. The package of claim 14 further comprising a second encapsulating material encapsulating the device die therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other.

19. The package of claim 1

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chang Chih-Yuan
• Wang Chuei-Tang
• Hsieh Jeng-Shien

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title