Vision-based wafer notch position measurement

Patent metadata

Field	Value
Publication number	US-9831110-B2
Application number	US-201514813948-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Jul 30, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A wafer alignment system includes an image capture device that captures an image of a wafer positioned on a pedestal. An image analysis module analyzes the image to detect an edge of the wafer and a notch formed in the edge of the wafer and calculates, based on a position of the notch, first and second edge positions corresponding to the edge of the wafer. An offset calculation module calculates an angular offset of the wafer based on the first position and the second edge positions. A system control module controls transfer of the wafer from the pedestal to a process cell based on the angular offset.

First claim

What is claimed is:

1. A wafer alignment system comprising:
an image capture device that captures an image of a wafer positioned on a pedestal;
an image analysis circuit that analyzes the image to detect an edge of the wafer as captured in the image and a notch formed in the edge of the wafer as captured in the image, and that calculates first and second edge positions corresponding to the edge of the wafer based on (i) a position of the detected notch and (ii) expected distances of the first and second edge positions from the position of the detected notch as captured in the image;
an offset calculation circuit that calculates an angular offset of the wafer based on the first edge position and the second edge position; and
a system control circuit that controls transfer of the wafer from the pedestal to a process cell based on the angular offset.

2. The wafer alignment system of claim 1 , wherein the first and second edge positions are a predetermined distance from the position of the detected notch in accordance with the expected distances.

3. The wafer alignment system of claim 1 , wherein, to calculate the angular offset, the offset calculation circuit compares the first and second edge positions to third and fourth edge positions.

4. The wafer alignment system of claim 3 , wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

5. The wafer alignment system of claim 3 , wherein the third and fourth edge positions correspond to an edge of a test wafer.

6. The wafer alignment system of claim 5 , wherein the image analysis circuit calculates the third and fourth edge positions using an image taken while the test wafer is arranged in a reference position on the pedestal.

7. The wafer alignment system of claim 5 , wherein the first, second, third, and fourth edge positions each correspond to coordinates within a field of view of the image capture device.

8. The wafer alignment system of claim 5 , further comprising a light source arranged on a side of the wafer opposite the image capture device, wherein the light source is arranged to project light past the wafer toward the image capture device.

9. The wafer alignment system of claim 8 , wherein the light source is arranged to illuminate a field of view of the image capture device.

10. The wafer alignment system of claim 1 , wherein the system control circuit adjusts a load position of the process cell based on the angular offset prior to transferring the wafer to the process cell.

11. A wafer alignment method comprising:
capturing an image of a wafer positioned on a pedestal;
analyzing the image to detect an edge of the wafer as captured in the image and a notch formed in the edge of the wafer as captured in the image;
calculating first and second edge positions corresponding to the edge of the wafer based on (i) a position of the detected notch and (ii) expected distances of the first and second edge positions from the position of the detected notch as captured in the image;
calculating an angular offset of the wafer based on the first edge position and the second edge position; and
controlling transfer of the wafer from the pedestal to a process cell based on the angular offset.

12. The wafer alignment method of claim 11 , wherein the first and second edge positions are a predetermined distance from the position of the detected notch in accordance with the expected distances.

13. The wafer alignment method of claim 11 , wherein calculating the angular offset includes comparing the first and second edge positions to third and fourth edge positions.

14. The wafer alignment method of claim 13 , wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

15. The wafer alignment method of claim 13 , wherein the third and fourth edge positions correspond to an edge of a test wafer.

16. The wafer alignment method of claim 15 , further comprising calculating the third and fourth edge positions using an image taken while the test wafer is arranged in a reference position on the pedestal.

17. The wafer alignment method of claim 15 , wherein the first, second, third, and fourth edge positions each correspond to coordinates within a field of view of an image capture device.

18. The wafer alignment method of claim 15 , further comprising, using a light source arranged on a side of the wafer opposite an image capture device, projecting light past the wafer toward the image capture device.

19. The wafer alignment method of claim 18 , wherein the light source is arranged to illuminate a field of view of the image capture device.

20. The wafer alignment method of claim 11 , further comprising adjusting a load position of the process cell based on the angular offset prior to transferring the wafer to the process cell.

Assignees

• Lam Res Corp

Inventors

• Francken Gustavo G
• Senn Brandon
• Thaulad Peter
• Chen Zhuozhi
• Lyons Richard K
• Dipietro Christian
• Bartlett Christopher M

Classifications

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title

• H10P72/57

  Mask-wafer alignment · CPC title

• H10P72/53 Primary

  using optical controlling means · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• Y10S901/47

  Optical · CPC title