Stress patterns to detect shorts in three dimensional non-volatile memory

Patent metadata

Field	Value
Publication number	US-9830998-B2
Application number	US-201514716794-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	May 19, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of non-volatile memory cells arranged in a three dimensional structure comprising a plurality of vertical columns with each vertical column of the plurality of vertical columns including multiple memory cells; and
a managing circuit in communication with the vertical columns, the managing circuit is configured to apply multiple different patterns of stress voltages to the plurality of vertical columns of non-volatile memory cells during a stress operation with different voltages applied to each vertical column of pairs of adjacent vertical columns, each pattern of stress voltages is configured to evoke different sets of defects between pairs of adjacent vertical columns, the memory cells are not programmed during the stress operation, the managing circuit is configured to test for defects in the pairs of adjacent vertical columns after applying the patterns of stress voltages by programming test data and sensing the test data the managing circuit is configured to test for defects by performing a separate test for each pattern of stress voltages, each separate test includes programming data to memory cells and reading back the data from the memory cells.

2. The apparatus of claim 1 , wherein:
the multiple different patterns of stress voltages include patterns of high and low stress voltages; and
for pairs of adjacent vertical columns, a pattern of stress voltages provides one vertical column with a high voltage and another vertical column with a low voltage.

3. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages by applying a first pattern of stress voltages; and
the managing circuit is configured to test for defects by programming a memory cell in each of the plurality of vertical columns with data that matches the first pattern of stress voltages, reading from the memory cell in each of the set of vertical columns and determining whether data read matches data programmed.

4. The apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells and the managing circuit are on a memory die;
the multiple different patterns of stress voltages are determined by the memory die; and
the applying multiple different patterns of stress voltages to the plurality of vertical columns and the test for defects are performed entirely on the memory die.

5. The apparatus of claim 4 , wherein:
the managing circuit includes a state machine; and
the state machine is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns and to test for defects.

6. The apparatus of claim 1 , wherein:
the managing circuit is configured to perform multiple program and erase cycles for the vertical columns of non-volatile memory cells; and
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns and to test for defects in response to and after the multiple program and erase cycles.

7. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns and to test for defects as part of an erase process for the vertical columns of non-volatile memory cells.

8. The apparatus of claim 1 , wherein:
the managing circuit is configured to perform a plurality of erase processes during user operation; and
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns and to test for defects in conjunction with a subset of the erase processes during user operation.

9. The apparatus of claim 1 , wherein:
the vertical columns of non-volatile memory cells are on a memory die;
the memory die includes a set of N I/O pins; and
the multiple different patterns of stress voltages include an arrangement of N signals that is repeated across the plurality of vertical columns.

10. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns of non-volatile memory cells and test for defects in the pairs of adjacent vertical columns during user operation.

11. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns of non-volatile memory cells and test for defects in the pairs of adjacent vertical columns after receiving a request to program data.

12. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns of non-volatile memory cells and test for defects in the pairs of adjacent vertical columns after every X program-erase cycles.

13. The apparatus of claim 1 , wherein:
the managing circuit is configured to apply the multiple different patterns of stress voltages to the plurality of vertical columns for longer in time than the managing circuit is configured to apply program pulses to the plurality of vertical columns.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pachamuthu Jayavel
• Magia Sagar
• Babariya Ankitkumar
• Sabde Jagdish

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/025 Primary

  in signal lines · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C29/06

  Acceleration testing · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title