Test data reporting during memory testing

Patent metadata

Field	Value
Publication number	US-9250992-B1
Application number	US-201414246854-A
Country	US
Kind code	B1
Filing date	Apr 7, 2014
Priority date	May 7, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

In some implementations, a built-in self-test (BIST) circuitry of a memory device is configured to perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated, enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error, detect an error in data read from the memory device after enabling error logging, and store information associated with the detected error.

First claim

What is claimed is:

1. A method comprising:
performing, by memory testing circuitry, an execution of a test sequence to test a memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated;
enabling error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error;
detecting an error in data read from the memory device after enabling error logging; and
storing information associated with the detected error, wherein storing the information comprises storing an address generated for reading the data associated with the detected error from a location of the memory device and storing a value of the modulo counter corresponding to the address generated for reading the data.

2. The method of claim 1 , wherein performing the execution of the test sequence to test the memory device comprises:
performing execution of the test sequence from a first address of the test sequence to a last address of the test sequence, uninterrupted, at an intended operating speed of the memory device.

3. The method of claim 2 , wherein performing the execution of the test sequence at the intended operating speed of the memory device comprises:
providing each address of the generated addresses to the memory device for a plurality of clock cycles.

4. The method of claim 1 , further comprising:
performing one or more other executions of the test sequence to test the memory device, wherein the previously detected error is associated with an execution of the one or more other executions, and the previously detected error is an intermittent error.

5. The method of claim 1 , further comprising:
for each of the addresses generated in accordance with the test sequence, combining the generated address and a corresponding value of the modulo counter to generate an error signature, wherein each error signature is different from other error signatures generated during the execution of the test sequence, and a maximum number of count values generated by the modulo counter is a relative prime of a number of memory locations accessed during the execution of the test sequence.

6. The method of claim 1 , further comprising:
unasserting an error logging enable signal during a previous execution to disable error logging when performing of the execution of the test sequence begins;
asserting the unasserted error logging enable signal when error logging is enabled; and
unasserting the asserted error logging enable signal to disable error logging in response to detecting the error.

7. The method of claim 1 , wherein the memory testing circuitry is built-in self-test (BIST) circuitry of the memory device, and the memory testing circuitry runs synchronously with the memory device.

8. An apparatus comprising:
a memory device; and
built-in self-test (BIST) circuitry of the memory device, the BIST circuitry configured to:
perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated,
enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error,
detect an error in data read from the memory device after enabling error logging, and
store information associated with the detected error, wherein storing the information comprises storing an address generated for reading the data associated with the detected error from a location of the memory device and storing a value of the modulo counter corresponding to the address generated for reading the data.

9. The apparatus of claim 8 , wherein the BIST circuitry is configured to perform the execution of the test sequence from a first address of the test sequence to a last address of the test sequence, uninterrupted, at an intended operating speed of the memory device.

10. The apparatus of claim 9 , wherein the BIST circuitry is configured to provide each address of the generated addresses to the memory device for a plurality of clock cycles.

11. The apparatus of claim 8 , wherein the BIST circuitry is configured to perform one or more other executions of the test sequence to test the memory device, wherein the previously detected error is associated with an execution of the one or more other executions, and the previously detected error is an intermittent error.

12. The apparatus of claim 8 , wherein the BIST circuitry is configured to combine, for each of the addresses generated in accordance with the test sequence, the generated address and a corresponding value of the modulo counter to generate an error signature, wherein each error signature is different from other error signatures generated during the execution of the test sequence, and a maximum number of count values generated by the modulo counter is a relative prime of a number of memory locations accessed by the BIST circuitry during the execution of the test sequence.

13. The apparatus of claim 8 , wherein the BIST circuitry is configured to:
unassert an error logging enable signal during a previous execution to disable error logging when performing of the execution of the test sequence begins;
assert the unasserted error logging enable signal when error logging is enabled; and
unassert the asserted error logging enable signal to disable error logging in response to detecting the error.

14. The apparatus of claim 8 , wherein the BIST circuitry runs synchronously with the memory device.

15. A system comprising:
an external test controller; and
a memory device that includes built-in self-test (BIST) circuitry, the BIST circuitry coupled to the external test controller, the BIST circuitry configured to:
receive an instruction from the external test controller to perform an execution of a test sequence to test the memory device,
perform the execution of the test sequence, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated,
enable error logging when a generated address and value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error,
detect an error in data read from the memory device after enabling error logging, and
store information associated with the detected error, wherein storing the information comprises storing an address generated for reading the data associated with the detected error from a location of the memory device and storing a value of the modulo counter corresponding to the address generated for reading the data,

wherein the external test controller is configured to:
read the stored information associated with the detected error from the BIST circuitry.

16. The system of claim 15 , wherein the BIST circuitry is configured to perform the execution of the test sequence from a first address of the test sequence to a last address of the test sequence, uninterrupted, at an intended operating speed of the memory device.

17. The system of claim 16 , wherein the BIST circuitry is configured to provide each address

Assignees

• Marvell Int Ltd

Inventors

• Tam Kit Sang
• Lee Winston
• Bateman Robert
• Mcgrath Kresten V
• Lippincott David

Classifications

• G06F2201/86

  Event-based monitoring · CPC title

• G11C29/20

  using counters or linear-feedback shift registers [LFSR] · CPC title

• G11C2029/1208

  Error catch memory · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G06F11/27

  Built-in tests · CPC title