Debug in a multicore architecture

Patent metadata

Field	Value
Publication number	US-9830241-B2
Application number	US-201514822667-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Sep 14, 2004
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

First claim

The invention claimed is:

1. A method of debugging a multicore processor system-on-a-chip (“SoC”) comprising a single chip including a thread management and allocation controller and a plurality of processing cores each associated with a controller client from a plurality of controller clients and one debug and trace unit from a plurality of debug and trace units, the method comprising:
receiving, by one or more of a plurality of controller clients from the thread management and allocation controller communicatively coupled to each of the controller clients, an interrupt comprising an input to a debug and trace unit corresponding to the controller client, each controller client associated with and communicatively coupled to a different processing core of the multicore processor;
halting, by the debug and trace unit corresponding to the controller client, processing of the processing core corresponding to the controller client in response to the interrupt;
in response to receiving the interrupt, accessing, by the controller client, a thread descriptor from a head of a dispatch queue associated with the processing core corresponding to the controller client, the thread descriptor comprising thread control information;
decoding, by the controller client, the thread control information;
configuring, by the controller client, the processing core associated with the controller client to execute a thread based on the thread control information;
executing, by the processing core, the thread, wherein the controller client is configured to perform at least one of: supplying data to the processing core during the execution of the thread, and monitoring resource utilization by the processing core during the execution of the thread; and
in response to a completion of the execution of the thread, outputting, by the corresponding processing core, a result of the execution of the thread.

2. The method of claim 1 wherein the result of the execution of the thread further comprises of at least one of creation of thread, issuance of a synchronization primitive or a combination of thread creation and synchronization.

3. The method of claim 1 , further comprising providing, by the controller client, out of band interfaces to the corresponding debug and trace unit for use as outputs for at least one of a run-time or a debug event.

4. The method of claim 1 , further comprising providing, by the controller client, out of band interfaces to the corresponding debug and trace unit using a standard interrupt as an input to the corresponding debug and trace unit.

5. The method of claim 1 , further comprising of implementing, by the controller client, a FIFO interface for communicating with at least one of the processing core and one or more system resources.

6. The method of claim 1 , wherein supplying data to the processing core comprises configuring the controller client to operate in a streaming mode.

7. The method of claim 6 , wherein supplying data in the streaming mode comprises streaming data from a system memory to the processing core.

8. The method of claim 1 , further comprising:
interpreting, by the controller client, configuration commands;
translating, by the controller client, the interpreted configuration commands into write cycles; and
issuing, by the controller client, the write cycles to the processing core during the execution of the thread.

9. The method of claim 1 , wherein the thread is executed in response to one of: receiving an explicit execute primitive or entering a data transferal state.

10. The method of claim 1 , wherein the controller client determines that the execution of the thread is complete in response to receiving at least one of a signal from the processing core or measuring an amount of data outputted by the processing core.

11. A multicore processor system-on-a-chip (“SoC”) architecture comprising a single chip including a thread management and allocation controller and a plurality of processing cores each associated with a controller client from a plurality of controller clients and a debug and trace unit from a plurality of debug and trace units, the controller client of each processing core comprising:
an input for receiving an interrupt from the thread management and allocation controller, wherein the interrupt comprises an input to a debug and trace unit corresponding to the controller client;
a debug and trace unit corresponding to the controller client for halting processing of the processing core associated with the controller client in response to the interrupt;
a plurality of sub blocks for interfacing the controller client with an associated shared memory to access a thread descriptor from a head of a dispatch queue associated with the processing core corresponding to the controller client, wherein the shared memory is accessed in response to receiving the interrupt, the thread descriptor comprising thread control information;
a decoder for decoding the thread control information; and
a finite state machine for configuring the processing core of the controller client to execute a thread based on the thread control information and output a result of the execution of the thread, wherein the finite state machine performs at least one of: supplying data to the processing core during the execution of the thread and monitoring resource utilization by the processing core during the execution of the thread.

12. The controller client of claim 11 wherein the result of the execution of the thread comprises of at least one of a creation of thread, an issuance of a synchronization primitive, or a combination of thread creation and synchronization.

13. The controller client of claim 11 , wherein the interrupt further provides out of band interfaces to the corresponding debug and trace unit for use as outputs for at least one of a run-time or a debug event.

14. The controller client of claim 11 , wherein the interrupt further provides out of band interfaces to the corresponding debug and trace unit using a standard interrupt as an input to the corresponding debug and trace unit.

15. The controller client of claim 11 , further comprising a FIFO interface for communicating with at least one of the processing core and one or more system resources.

16. The controller client of claim 11 , wherein supplying data to the processing core comprises configuring the controller client to operate in a streaming mode.

17. The controller client of claim 16 , wherein supplying data in the streaming mode comprises streaming data from a system memory to the processing core.

18. The controller client of claim 11 , wherein the finite statement machine further:
interprets configuration commands;
translates the interpreted configuration commands into write cycles; and
issues the write cycles to the corresponding processing core during the execution of the thread.

19. The controller client of claim 11 , wherein the thread is executed by the processing core in response to one of: receiving an explicit execute primitive or entering a data transferal state.

20. The controller client of claim 11 , wherein the finite state machine further determines that the execution of the thread is complete in response to receiving at least one of a signal from the processing core or measuring an amount of data outputted by the processing core.

Assignees

• Synopsys Inc
• Fujitsu Semiconductor Ltd

Inventors

• Lippett Mark David
• Oung Ayewin

Classifications

• G06F11/2242

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title