Power saving systems and methods for Universal Serial Bus (USB) systems

Patent metadata

Field	Value
Publication number	US-9829958-B1
Application number	US-201615150586-A
Country	US
Kind code	B1
Filing date	May 10, 2016
Priority date	May 10, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

First claim

What is claimed is:

1. A method for reducing power consumption in a Universal Serial Bus (USB) physical layer (PHY) during a U3 power state, the method comprising:
during a U3 power state, receiving a reference clock signal at a USB PHY;
during the U3 power state, waking a medium frequency clock in the USB PHY on receipt of an edge in the reference clock signal;
during the U3 power state and as a function of operation of the medium frequency clock, waking a signal detection circuit; and
using the signal detection circuit, detecting a low frequency periodic signal (LFPS) on a line.

2. The method of claim 1 , wherein receiving the reference clock signal comprises receiving a thirty-two kilohertz (32 kHz) reference clock signal.

3. The method of claim 1 , wherein receiving the reference clock signal comprises receiving the reference clock signal from a power management integrated circuit (PMIC) having a crystal oscillator.

4. The method of claim 1 , further comprising entering the U3 power state.

5. The method of claim 4 , further comprising turning off the signal detection circuit concurrent with entrance into the U3 power state.

6. The method of claim 1 , wherein waking the medium frequency clock comprises waking a frequency locked loop (FLL) clock source.

7. The method of claim 1 , further comprising placing the medium frequency clock into a low power state when entering the U3 power state.

8. The method of claim 1 , wherein waking the medium frequency clock in the USB PHY on the receipt of the edge in the reference clock signal comprises waking the medium frequency clock on a rising edge.

9. The method of claim 1 , wherein waking the medium frequency clock in the USB PHY on the receipt of the edge in the reference clock signal comprises waking the medium frequency clock on a falling edge.

10. The method of claim 1 , further comprising, on detection of the LFPS, waking the USB PHY to a U0 active power state.

11. The method of claim 10 , wherein waking the USB PHY to the U0 active power state comprises generating an interrupt at a control system within the USB PHY and passing the interrupt to a USB PHY controller.

12. The method of claim 1 , wherein waking the medium frequency clock comprises waking the medium frequency clock for about four microseconds.

13. The method of claim 12 , wherein detecting the LFPS on the line comprises sampling the line for about one microsecond.

14. The method of claim 12 , wherein waking the medium frequency clock comprises allowing the medium frequency clock to settle for about two microseconds of the about four microseconds.

15. A Universal Serial Bus (USB) physical layer (PHY), comprising:
an input configured to receive a reference clock signal;
a line input configured to receive a low frequency periodic signal (LFPS);
a medium frequency clock;
a signal detection circuit configured to detect the LFPS on the line input; and
a control system configured to:
during a U3 low power state, wake the medium frequency clock on receipt of an edge in the reference clock signal;
during the U3 low power state and based on the receipt of waking of the medium frequency clock, wake the signal detection circuit;
receive an indication from the signal detection circuit that the LFPS was detected on the line input.

16. The USB PHY of claim 15 , wherein the medium frequency clock comprises a frequency locked loop (FLL) clock source.

17. The USB PHY of claim 15 , wherein the reference clock signal comprises a thirty-two kilohertz (32 kHz) clock signal.

18. The USB PHY of claim 15 , wherein the control system is further configured to turn off the signal detection circuit concurrent with entrance into the U3 low power state.

19. The USB PHY of claim 15 , wherein the control system is further configured to place the medium frequency clock into a low power state when entering the U3 low power state.

20. The USB PHY of claim 15 , wherein the control system is further configured to, on detection of the LFPS, output an interrupt indicating that a USB PHY controller is to wake the USB PHY to a U0 active power state.

21. The USB PHY of claim 15 , wherein the control system is configured to wake the medium frequency clock for about four microseconds.

22. The USB PHY of claim 21 , wherein the signal detection circuit is configured to sample the line input for the LFPS for about one microsecond after waking.

23. The USB PHY of claim 15 integrated into an integrated circuit (IC).

24. The USB PHY of claim 15 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a server; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

25. A Universal Serial Bus physical layer (PHY), comprising:
a means for receiving a reference clock signal;
a means for receiving a low frequency periodic signal (LFPS);
a medium frequency clock;
a means for detecting the LFPS on the means for receiving the LFPS; and
a control system configured to:
during a U3 low power state, wake the medium frequency clock on receipt of an edge in the reference clock signal;
during the U3 low power state and based on the receipt of waking of the medium frequency clock, wake the means for detecting the LFPS;
receive an indication from the means for detecting the LFPS that the LFPS was detected on the means for receiving the LFPS.

Assignees

• Qualcomm Inc

Inventors

• Winemiller Chad Everett
• Boyette Jon Raymond
• Deans Russell Coleman
• Zhu Zhi

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• G06F1/3278 Primary

  Power saving in modem or I/O interface · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title

• G06F1/3215

  Monitoring of peripheral devices · CPC title