Method for power saving during standby mode in the physical layer block for the serial data communication interface

Patent metadata

Field	Value
Publication number	US-9009510-B2
Application number	US-201313737803-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 13, 2012
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

A semiconductor device includes a detector that receives an input signal whose characteristics fluctuate depend on the standby mode state, compares the input signal amplitude with a specific threshold amplitude, and outputs a detector output signal that shows whether or not the amplitude of the applicable input signal is above the specified threshold amplitude; and an intermittent operation control circuit that along with receiving the detector output, also receives a first signal showing which mode among the multiple standby mode states is in, and sets the detector to the continuously on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector depend on the characteristics of the input signal in the mode shown by the first signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a detector to receive an input signal whose characteristics fluctuate according to the standby mode state, compare the amplitude of the applicable signal with a specified threshold amplitude, and outputs a detector output showing whether or not the amplitude of the applicable signal is above a specified threshold amplitude; and
an intermittent operation control circuit that along with receiving the detector output, also receives a first signal showing which mode among the multiple modes the standby mode state is in, and sets the detector to the on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector according to the characteristics of the input signal in the mode shown by the applicable first signal.

2. The semiconductor device according to claim 1 ,
wherein the intermittent operation control circuit sets the detector to the on (enable) mode state across a specified period in a cycle according to the maximum burst length of the input signal in the mode shown by the first signal, and sets the detector to the off mode state across all other periods.

3. The semiconductor device according to claim 2 ,
wherein the intermittent operation control circuit sets the detector to the on (enable) mode state spanning a specified period in a cycle from half the maximum burst length to the applicable maximum burst length of the input signal in the mode shown by the first signal, and sets the detector to the off (disable) mode state across all other periods.

4. The semiconductor device according to claim 1 , further comprising:
an oscillator to supply clock signals,
wherein besides dividing a clock signal to generate multiple frequency-divided clock signals, the intermittent operation control circuit generates signals for intermittently operating the detector by obtaining the logical product of the frequency-divided clock signals.

5. The semiconductor device according to claim 1 ,
wherein the input signal is a LFPS (Low Frequency Periodic Signaling) signal sent from a USB (Universal Serial Bus) device.

6. The semiconductor device according to claim 5 ,
wherein the detector and the intermittent operation control circuit are both formed in the physical layer.

7. The semiconductor device according to claim 5 , further comprising:
a register containing information showing which mode among the standby mode state is in,
wherein the intermittent operation control circuit receives a first signal from the register.

8. The semiconductor device according to claim 5 ,
wherein the physical layer includes the detector, and
wherein the link layer includes the intermittent operation control circuit.

9. The semiconductor device according to claim 1 ,
wherein the intermittent operation control circuit receives a second signal showing whether or not the detector circuit should be operated by normal operation or should be operated by intermittent operation, and when the input signal is above the specified threshold amplitude, or the applicable second signal shows the detector should be operated by normal operation, the detector circuit is set to the operation state, and in all other cases, the detector is set to the intermittent operation state.

10. The semiconductor device according to claim 9 ,
wherein along with identifying the standby mode state based on the enable signal for the PLL circuit from the link layer instead of utilizing the first signal and the second signal, the intermittent operation control circuit decides whether or not to operate the detector by normal operation or by intermittent operation.

11. The semiconductor device according to claim 9 ,
wherein the intermittent operation control circuit identifies the standby mode state based on the enable signal for the PLL circuit from the link layer, instead of utilizing the first signal.

12. The semiconductor device according to claim 9 ,
wherein along with identifying the standby mode state based on the enable signal for the PLL circuit from the link layer instead of utilizing the first signal and the second signal, the intermittent operation control circuit decides whether or not to operate the detector by normal operation or by intermittent operation based on the enable signal for the transmitter-receiver circuit.

13. The semiconductor device according to claim 9 ,
wherein the intermittent operation control circuit identifies the standby mode state based on the enable signal for the PLL circuit and the enable signal for the transmitter-receiver circuit from the link layer instead of utilizing the first signal.

14. The control method for a semiconductor device comprising:
comparing the amplitude of an input signal whose characteristics fluctuate according to the standby mode state with a specified threshold amplitude, and deciding by way of the detector whether or not the amplitude of the applicable input signal is above a specified threshold amplitude;
receiving a first signal showing which mode among the standby mode state is in; and
after the steps above, setting the detector to the on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operating the detector depend on the characteristics of the input signal in the mode shown by the first signal.

15. The control method for a semiconductor device according to claim 14 comprising:
setting the detector to the on (enable) mode state spanning a specified period in a cycle according to the maximum burst length of the input signal in the mode shown by the first signal, and setting the detector to the off (disable) mode state spanning all other periods.

16. The control method for a semiconductor device according to claim 15 , comprising:
setting the detector to the on (enable) mode state spanning a specified period in a cycle from half the maximum burst length to the maximum burst length of the input signal in the mode shown by the first signal, and setting the detector to the off (disable) mode state spanning all other periods.

Assignees

• Renesas Electronics Corp

Inventors

• Tan Kenzo

Classifications

• G06F1/3278 Primary

  Power saving in modem or I/O interface · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• Y02B60/126

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title