Low sweetness alcoholic beverage containing gin
US-2025059480-A1 · Feb 20, 2025 · US
US9829382B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9829382-B2 |
| Application number | US-201314647906-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 21, 2013 |
| Priority date | Sep 5, 2013 |
| Publication date | Nov 28, 2017 |
| Grant date | Nov 28, 2017 |
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A system for measuring a sensor having two terminals includes first and second transistors with first and second control signal inputs connected to the sensor terminals. The system further includes a current divider including a reference current input, a current divider control input and first and second current outputs connected to the first and second transistors. First and second load circuits are connected to the first and second transistors at first and second differential output nodes. First and second integrator circuits are connected to the first and second differential output nodes. A comparator is driven by first and second differential output nodes. The comparator output controls a digital filter. A value of the a current divider control signal driving the current divider control input depends at least indirectly from the digital filter output.
Opening claim text (preview).
The invention claimed is: 1. A system for measuring a sensor, the sensor including a first sensor terminal and a second sensor terminal, comprising: a first transistor including a third terminal, a fourth terminal and a fifth terminal, the third terminal being a first transistor control terminal and connected to the first sensor terminal; a second transistor including a sixth terminal, a seventh terminal and a eighth terminal, the sixth terminal being a second transistor control terminal and connected to the second sensor terminal; a current divider including a reference current input, a control input, a first current divider output and a second current divider output, wherein the first current divider output is connected to the fourth terminal of the first transistor and the second current divider output is connected to the seventh terminal of the second transistor; a reference current source connected to the reference current input; a first load circuit connected to the fifth terminal of the first transistor at a first differential output node; a second load circuit connected to the eighth terminal of the second transistor at a second differential output node; a first integrating circuit connected to the first differential output node, and configured to integrate a first differential output signal; a second integrating circuit connected to the second differential output node, and configured to integrate a second differential output signal; a comparator including a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is connected to the first differential output node and the second comparator input is connected to the second differential output node; and a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator input is driven by the comparator output; wherein: a value of a current divider control signal driving the current divider control input depends from the digital integrator output. 2. The system of claim 1 , wherein: the first and second load circuits include respectively first and second load resistors configured to provide a load to the respective first and second differential output nodes. 3. The system of claim 1 , wherein: the first and second load circuits include respectively first and second load current sources configured to provide a load to the respective first and second differential output nodes. 4. The system of claim 1 ; wherein the current divider further includes: a resistor string including a plurality of resistors arranged in a series configuration including a plurality of taps, the plurality of taps including the first current divider output on a first end of the resistor string, the second current divider output on a second end of the resistor string, and a plurality of middle taps arranged respectively between pairs of adjacent resistors in the resistor string; and an analog multiplexer arranged to connect one of the plurality of taps to the reference current input, the one of the plurality of taps selected based on the value of the current divider control signal. 5. The system of claim 1 , wherein: the first and second integrating circuits include respectively first and second integrated filters. 6. The system of claim 1 , wherein: the first and second integrating circuits include respectively first and second integration capacitors. 7. The system of claim 6 , wherein the sensor includes a passive infrared detector. 8. The system of claim 1 , further comprising: a digital filter having a digital filter input and a digital filter output, the digital filter input driven by the digital integrator output; wherein: the value of the current divider control signal depends directly from the digital filter output. 9. The system of claim 1 ; wherein: the digital integrator includes an up/down count; and a value of the comparator output controls a direction of counting of the up/down counter. 10. The system of claim 9 , wherein: a rate of at least one of incrementing and decrementing the up/down counter is predetermined. 11. The system of claim 9 , wherein: a rate of at least one of incrementing and decrementing the up/down counter is programmable.
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