Charge-compensation device

Patent metadata

Field	Value
Publication number	US-9825165-B2
Application number	US-201514973385-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Dec 22, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length. The second compensation regions have, in a horizontal direction parallel to the first surface, a horizontal width which decreases with an increasing vertical distance from the first surface and with a decreasing horizontal distance from the edge.

First claim

The invention claimed is:

1. A charge-compensation semiconductor device, comprising:
a semiconductor body comprising:
a first surface;
a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface;
an active area, a peripheral area arranged between the active area and the lateral edge;
a drift region;
compensation regions each of which forms a respective pn-junction with the drift region, wherein the compensation regions form in the active area a lattice comprising a first base vector having a first length, and wherein, in a vertical cross-section perpendicular to the first surface, a horizontal width of the compensation regions decreases in the peripheral area with an increasing vertical distance from the first surface and with a decreasing horizontal distance from the edge;
a source metallization arranged on the first surface in Ohmic contact with the compensation regions in the active area; and
a drain metallization opposite to the source metallization and in Ohmic contact with the drift region,
wherein a first doping-bias as a function of a horizontal distance from the lateral edge changes its sign from minus one to one, the first doping-bias being defined as an integral obtainable by integrating a first function along a horizontal line arranged at the horizontal distance from the lateral edge, crossing at least one of the pn-junctions, and having a length equal to the first length or an integer multiple thereof, the first function being defined as a difference between a concentration of p-type dopants in the semiconductor body and a concentration of n-type dopants in the semiconductor body.

2. The charge-compensation semiconductor device of claim 1 , wherein the compensation regions have in the active area a further horizontal width which decreases with increasing vertical distance from the first surface.

3. A charge-compensation semiconductor device, comprising:
a semiconductor body comprising a semiconductor material, a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, and a drift region comprising first dopants providing a first number of first charge carriers per unit in the semiconductor material;
a source metallization arranged on the first surface; and
a drain metallization arranged opposite to the source metallization and in Ohmic contact with the drift region;
wherein the semiconductor body further comprises, in a vertical cross-section substantially perpendicular to the first surface, compensation regions which alternate with portions of the drift region in the active area and in the peripheral area, have at least in the active area a first horizontal pitch, and comprise second dopants providing a second number of second charge carriers per unit in the semiconductor material, the second charge carriers being different to the first charge carriers,
wherein the compensation regions of the active area are in Ohmic contact with the source metallization, and
wherein a first doping-bias as a function of a horizontal distance from the active area changes its sign from one to minus one, the first doping-bias being defined as an integral obtainable by integrating a first function along a horizontal line arranged in the peripheral area at the horizontal distance from the active area and having a length equal to the first horizontal pitch or an integer multiple thereof, the first function being defined as a difference between a concentration of the second dopants multiplied by the second number and a concentration of the first dopants multiplied by the first number.

4. The charge-compensation semiconductor device of claim 3 , wherein the first doping-bias is a monotonically decreasing function of the horizontal distance.

5. The charge-compensation semiconductor device of claim 3 , wherein a second doping-bias as a function of a vertical distance from the first surface changes its sign from one to minus one, the second doping-bias being defined as an integral obtainable by integrating the first function along a further horizontal line crossing one of the compensation regions of the active area at the vertical distance from the first surface and having a length equal to the first horizontal pitch or an integer multiple thereof.

6. The charge-compensation semiconductor device of claim 5 , wherein the second doping-bias is a monotonically decreasing function of the vertical distance.

7. The charge-compensation semiconductor device of claim 5 , wherein the compensation regions of the active area extend in a vertical direction from a first vertical distance to a second vertical distance, and wherein the second doping-bias is substantially linear between the first vertical distance and the second vertical distance.

8. The charge-compensation semiconductor device of claim 3 , further comprising a conductive drain ring arranged on the first surface and in Ohmic contact with the drain metallization, and a conductive gate ring arranged on the first surface and between the conductive drain ring and the active device area, wherein the conductive gate ring extends in the vertical cross-section to a first horizontal distance, wherein the conductive drain ring extends in the vertical cross-section and the peripheral area to a second horizontal distance (d x3 , d x4 ), and wherein the first doping-bias is substantially linear between the first horizontal distance and the second horizontal distance.

9. The charge-compensation semiconductor device of claim 3 , wherein a first horizontal width of the compensation regions decreases with the vertical distance; and/or wherein a second horizontal width of the compensation regions in the peripheral area decreases with a decreasing distance from the edge.

10. The charge-compensation semiconductor device of claim 3 , wherein a distance of the horizontal line from the first surface is less than about two times the first horizontal pitch.

11. The charge-compensation semiconductor device of claim 8 , wherein, from a plan view perspective of the device in which outlines of the compensation regions are projected onto the first surface, several compensation regions in the peripheral area cross the conductive gate ring and the conductive drain ring and have a decreasing horizontal width between the conductive gate ring and the conductive drain ring.

12. The charge-compensation semiconductor device of claim 3 , wherein each of the compensation regions in the active area and each of the compensation regions in the peripheral area is arranged in a respective tapered trench.

13. A charge-compensation semiconductor device, comprising:
a semiconductor body comprising a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, and a drift region comprising a semiconductor material and first dopants providing a first number of first charge carriers per unit in the semiconductor material;
a source metallization arranged on the first surface; and
a drain metallization arranged opposite to the source metallization and in Ohmic contact with the drift region;
wherein the semiconductor body further comprises, in horizontal cross-sections substantially parallel to the first surface, compensation regions each of which forms a pn-junction with the drift region and comprises the semiconductor material and second dopants providing a second number of second cha

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Schmitt Markus
• Voerckel Andreas

Classifications

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H01L29/4238

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic