Power MOSFET, an IGBT, and a power diode

Patent metadata

Field	Value
Publication number	US-9825163-B2
Application number	US-201514855980-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Aug 12, 2011
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

First claim

What is claimed is:

1. A semiconductor device including a power MOSFET having a super-junction structure, comprising:
a semiconductor substrate having a first main surface and a second main surface opposite each other, the semiconductor substrate having an active cell region in which the power MOSFET is formed and a peripheral region over the first main surface, the peripheral region surrounding the active cell region in a plan view;
a gate electrode disposed over the first main surface;
a source electrode disposed over the first main surface;
a drain electrode disposed over the second main surface;
a plurality of first N-columns and a plurality of first P-columns disposed in the first main surface;
a ring-shaped field plate disposed over the first main surface in to surround the active cell region in the plan view, the field plate including a pair of first straight portions opposite each other and a pair of second straight portions opposite each other, each of the pair of the first portions and each of the pair of second portions are disposed in the peripheral region and connected via a plurality of corner portions: and
one elongated, or a plurality of dot-like, first contact holes disposed over the first main surface and coupling the field plate and a first one of the plurality of the first P-columns;
wherein the one elongated, or the plurality of dot-like, first contact holes and a first one of the first straight portions of the field plate are overlapped in the plan view, and wherein the one elongated, or the plurality of dot-like, first contact holes extend substantially along a majority of a length of the first one of the first straight portions in the plan view,
wherein the one elongated, or the plurality of dot-like, first contact holes do not overlap with the corner portions of the field plate in the plan view,
wherein the field plate has a first ohmic contact part that extends over the first one of the plurality of the first P-columns in the peripheral region where the first one of the first straight portions of the field plate and the first one of the plurality of the first P-columns are in ohmic contact via the one elongated, or the plurality of dot-like, first contact holes, and
wherein the field plate does not contact the first N-columns and the first P-columns in any of the corner portions.

2. The semiconductor device according to claim 1 ,
wherein the field plate is disposed in such a manner as to surround the source electrode in the plan view.

3. The semiconductor device according to claim 1 ,
wherein each of the plurality of first N-columns is disposed parallel to each of the plurality of first P-columns.

4. The semiconductor device according to claim 1 , further comprising:
a plurality of second P-columns disposed in the first main surface in the peripheral region,
wherein each of the plurality of the second P-columns is disposed perpendicular to each of the plurality of the first N-columns and P-columns.

5. The semiconductor device according to claim 4 , further comprising: one elongated, or a plurality of dot-like, second contact holes disposed over the first main surface and coupling the field plate and a second one of the plurality of the second P-columns,
wherein the one elongated, or the plurality of dot-like, second contact holes and a first one of the second straight portions of the field plate are overlapped in the plan view, and wherein the one elongated, or the plurality of dot-like, second contact holes extend substantially along a majority of a length of the first one of the second straight portions in the plan view,
wherein the field plate has a second ohmic contact part that extends over the second one of the plurality of the first P-columns in the peripheral region where the first one of the first straight portions of the field plate and the second one of the plurality of the first P-columns are in ohmic contact via the one elongated, or the plurality of dot-like, second contact holes.

6. The semiconductor device according to claim 5 ,
wherein the one elongated, or the plurality of dot-like, second contact holes do not overlap with the corner portions of the field plate in the plan view.

Assignees

• Renesas Electronics Corp

Inventors

• Tamaki Tomohiro

Classifications

• H01L29/66727

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic

• H01L29/7811 Primary

  Electricity · mapped topic

• H01L29/404

  Electricity · mapped topic

• H01L29/7396

  Electricity · mapped topic