Packaging solutions for devices and systems comprising lateral GaN power transistors

Patent metadata

Field	Value
Publication number	US-9824949-B2
Application number	US-201615197861-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Mar 11, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

First claim

The invention claimed is:

1. A semiconductor device structure comprising an assembly of:
a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a first leadframe layer and a second leadframe layer;
the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
the GaN die being sandwiched between the first and second leadframe layers;
the first leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die;
the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material;
the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the first leadframe layer by low inductance interconnections;
a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the source, drain and gate of the lateral GaN transistor; and
wherein said external contact pads for the source, drain and gate contacts are parts of the first leadframe layer and are provided on a front-side of the package body and the thermal pad is provided on a back-side of the package body.

2. The device structure of claim 1 , wherein one of the first and second leadframe layers further comprises a source clip portion, laterally spaced from the die substrate, which vertically interconnects the second leadframe layer and the source portion of the first leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source.

3. The device structure of claim 2 , wherein
the source portion of the first leadframe comprises the external source pad and a plurality of source fingers extending laterally from the source pad, and the drain portion of the first leadframe comprises the external drain pad and a plurality of drain fingers extending laterally from the drain pad,
the source pad and the drain pad having a first thickness and the source and drain fingers having a second thickness less than the first thickness of the source pad and drain pad.

4. The device structure of claim 3 , wherein the source fingers and drain fingers are half-etched, and
the over-molding of encapsulation comprises a first encapsulation on the front-side and periphery of the package body, and a second encapsulation on an area of a back-side of the package overlying the half-etched source fingers and drain fingers.

5. The device structure claim 2 , wherein the semiconductor substrate of the GaN die comprises a silicon substrate, and wherein the first and second leadframe layers comprise copper and/or a copper alloy with high electrical and thermal conductivity.

6. The device structure of claim 5 , wherein the attachment material attaching the back surface of the GaN die to the die-attach area of the second leadframe layer comprises a layer of sintered silver.

7. The device structure of claim 2 , wherein the semiconductor substrate of the GaN die comprises a silicon carbide substrate, wherein the first and second leadframe layers each comprise copper and/or a copper alloy with high electrical and thermal conductivity.

8. The device structure of claim 7 , wherein the attachment material attaching the back surface of the GaN die to the die-attach area of the second leadframe layer comprises a layer of sintered silver.

9. The device structure of claim 2 , wherein the low inductance interconnections comprise metal bump or metal post connections.

10. The device structure of claim 9 , wherein the metal bump or metal post connections comprise copper pillars.

11. The device structure of claim 4 , wherein the semiconductor substrate of the GaN die comprises a silicon substrate, the first and second leadframe layers comprise copper and/or a copper alloy with high electrical and thermal conductivity, the attachment material comprises sintered silver, and the low inductance interconnections comprises solder tipped copper pillars.

12. The device structure of claim 2 , wherein the first and second leadframe layers further comprise registration means for laterally and vertically aligning the first and second leadframe layers during assembly.

13. The device structure of claim 12 , wherein the registration means comprises one of:
a) tabs on the first leadframe layer and corresponding slots in the second leadframe layer, the tabs and slots inter-engaging to mutually align the first and second leadframes;
b) tabs on the second leadframe layer and corresponding slots in the first leadframe layer, the tabs and slots inter-engaging to mutually align first and second leadframes; and
c) a combination thereof.

14. The device structure of claim 2 , further comprising a second GaN die or other semiconductor die co-packaged with the said GaN die and interconnected therewith by said first and second leadframe layers.

15. A method of fabricating a semiconductor device structure comprising an assembly of:
a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers for encapsulation within a package body, the method comprising:
providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
providing a first leadframe layer and a second leadframe layer;
the first leadframe layer being patterned to provide source, drain and gate portions, the source portion comprising an external source pad and a plurality of source fingers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain fingers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die;
the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die,
at least one of the first and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the first leadframe layer;
attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material;
providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected;
mutually positioning the first and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween;
processing the respective bump connections, post connections and the attachment material to vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the first copper lea

Assignees

• Gan Systems Inc

Inventors

• Mcknight-Macneil Cameron
• Klowak Greg P
• Mizan Ahmad
• Coates Stephen

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title