Methods for producing semiconductor devices

Patent metadata

Field	Value
Publication number	US-9824927-B2
Application number	US-201615346746-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Jul 22, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

First claim

What is claimed is:

1. A method for producing a semiconductor device, the method comprising:
providing a semiconductor layer disposed on a first carrier;
forming a device layer on the semiconductor layer;
forming one or more semiconductor devices with at least one semiconductor device formed on or in the device layer;
applying a second carrier to the device layer;
removing the first carrier;
applying a metal layer over a side of the device layer facing away from the second carrier;
dicing the metal layer, the device layer, and the second carrier so as to form at least one individual semiconductor chip;
mounting the at least one individual semiconductor chip on a third carrier; and
removing the second carrier from the at least one mounted individual semiconductor chip,
wherein the semiconductor layer is a continuous unpatterned layer.

2. The method of claim 1 , further comprising removing the semiconductor layer before applying the metal layer.

3. The method of claim 1 , wherein forming the device layer comprises forming an epitaxial layer on the semiconductor layer.

4. The method of claim 1 , wherein the semiconductor layer is formed on the first carrier through a SMART cut process.

5. The method of claim 1 , wherein the second carrier is substantially transparent.

6. The method of claim 1 , wherein the one or more semiconductor devices comprise one or more power devices.

7. The method of claim 1 , wherein the semiconductor layer has a thickness of less than or equal to 100 μm.

8. The method of claim 1 , wherein semiconductor layer comprises silicon.

9. The method of claim 1 , wherein semiconductor layer comprises at least one of silicon carbide and gallium nitride.

10. The method of claim 1 , wherein device layer comprises silicon.

11. The method of claim 1 , wherein device layer comprises at least one of silicon carbide and gallium nitride.

12. The method of claim 1 , wherein the semiconductor layer has a greater or equal doping concentration to the device layer.

13. The method of claim 1 , wherein the third carrier is an electrically conductive carrier.

14. The method of claim 1 , further comprising, after applying the metal layer and before dicing, mounting the second carrier, the device layer, and the metal layer to a foil so that an exposed surface of the second carrier faces away from the foil.

15. The method of claim 14 , wherein the foil is not diced.

16. A method for producing a semiconductor device, the method comprising:
providing a semiconductor layer disposed on a first carrier;
forming a device layer on the semiconductor layer;
forming one or more semiconductor devices with at least one semiconductor device formed on or in the device layer;
applying a second carrier to the device layer;
removing the first carrier;
applying a metal layer to the semiconductor layer over a side of the device layer facing away from the second carrier;
dicing the metal layer, the device layer, the semiconductor layer, and the second carrier so as to form at least one individual semiconductor chip;
mounting the at least one individual semiconductor chip on a third carrier; and
removing the second carrier from the at least one mounted individual semiconductor chip.

17. The method of claim 16 , wherein the one or more semiconductor devices comprise one or more power devices.

18. The method of claim 16 , wherein device layer comprises at least one of silicon carbide and gallium nitride.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Voerckel Andreas

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07307

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title