Memory module with timing-controlled data paths in distributed data buffers

Patent metadata

Field	Value
Publication number	US-9824035-B2
Application number	US-201715426064-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	Jul 16, 2009
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

First claim

We claim:

1. A memory module operable to communicate with a memory controller via a memory bus, the memory bus including signal lines, the signal lines including a set of control/address signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising:
a module board having edge connections for coupling to respective signal lines in the memory bus;
a module control device mounted on the module board and configured to receive memory command signals for a first memory operation from the memory controller via the set of control/address signal lines and to output module command signals and module control signals in response to the memory command signals; and
memory devices mounted on the module board and configured to perform the first memory operation in response to the module command signals, the memory devices including a plurality of sets of memory devices corresponding to respective sets of the plurality of sets of data/strobe signal lines; and
a plurality of buffer circuits mounted on the module board in positions corresponding to respective sets of the plurality of sets of data/strobe signal lines, wherein each respective buffer circuit of the plurality of buffer circuits is coupled between a respective set of data/strobe signal lines and a respective set of memory devices, the each respective buffer circuit including data paths for transmitting respective data and strobe signals associated with the first memory operation and logic configured to respond to the module control signals by enabling the data paths, wherein the logic is further configured to obtain timing information based on one or more signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the respective data and strobe signals on the data paths in accordance with the timing information.

2. The memory module of claim 1 , wherein the first memory operation is a memory read operation and the second memory operation is a memory write operation.

3. The memory module of claim 2 , wherein the each respective buffer circuit includes a delay control circuit configured to determine, during the memory write operation, a time interval between receiving a first signal from the module control device and receiving a second signal from the memory controller, and wherein the timing information includes the time interval.

4. The memory module of claim 3 , wherein the each respective buffer circuit is further configured to receive a module clock signal and further includes a clock regeneration circuit configure to generate a local clock signal having a programmable phase relationship with the module clock signal, wherein the each respective buffer circuit is further configured to output the local clock signal to the respective set of memory devices.

5. The memory module of claim 3 , wherein each of the plurality of buffer circuits has a data width of 1 byte, and wherein each of the memory devices has a data width of 1 byte.

6. The memory module of claim 2 , wherein the memory devices are arranged in a plurality of ranks and the respective set of memory devices include one memory device from each of the plurality of ranks, and wherein the module command signals include chip select signals that select one memory device in the respective set of memory devices to output the respective data and strobe signals.

7. The memory module of claim 3 , wherein each of the plurality of buffer circuits has a data width of 1 byte, and wherein each of the memory devices has a data width of 4 bits.

8. The memory module of claim 7 , wherein the memory devices are arranged in a plurality of ranks and the respective set of memory devices include two memory devices from each of the plurality of ranks, and wherein the module command signals include chip select signals that select two memory devices in the respective set of memory devices to output the respective data and strobe signals, the two memory devices being in a same rank.

9. The memory module of claim 1 , wherein the each respective buffer circuit is further configured to receive a module clock signal from the module control device and further includes a receiver circuit for each of the module control signals, the receiver circuit including a metastability detection circuit configured to determine a metastability condition in the each of the module control signals with respect to the module clock signal.

10. The memory module of claim 1 , wherein each of the plurality of buffer circuits has a data width of 1 byte, and wherein each of the memory devices has a data width of 1 byte.

11. The memory module of claim 10 , wherein the memory devices are arranged in a plurality of ranks and the respective set of memory devices include one memory device from each of the plurality of ranks, and wherein the module command signals include chip select signals that select one memory device in the respective set of memory devices to receive or output the respective data and strobe signals.

12. The memory module of claim 1 , wherein each of the plurality of buffer circuits has a data width of 1 byte, and wherein each of the memory devices has a data width of 4 bits.

13. The memory module of claim 12 , wherein the memory devices are arranged in a plurality of ranks and the respective set of memory devices include two memory devices from each of the plurality of ranks, and wherein the module command signals include chip select signals that select two memory devices in the respective set of memory devices to receive or output the respective data and strobe signals, the two memory devices being in a same rank.

14. The memory module of claim 1 , wherein the each respective buffer circuit is further configured to receives a module clock signal and further includes a clock regeneration circuit configured to generate a local clock signal having a programmable phase relationship with the module clock signal, wherein the each respective buffer circuit is configured to output the local clock signal to the respective set of memory devices.

15. The memory module of claim 14 , wherein the data paths include a first data path for transmitting a strobe signal among the respective data and strobe signals, the first data path including a sampler that samples the strobe signal in accordance with the local clock signal.

16. The memory module of claim 15 , wherein the data paths include a second data path for transmitting a first data signal among the data and strobe signals, the second data path including a sampler that samples the first data signal in accordance with the sampled strobe signal.

17. The memory module of claim 14 , wherein each of the plurality of buffer circuits has a data width of 1 byte , and wherein each of the memory devices has a data width of 1 byte.

18. The memory module of claim 17 , wherein the memory devices are arranged in a plurality of ranks and the respective set of memory devices include one memory device from each of the plurality of ranks, and wherein the module command signals include chip select signals that select one memory device in the respective set of memory devices to output or receive the respective data and strobe signals in accordance with the local clock signal.

19. The memory module of claim 14 , wherein each of the plurality of buffer circuits has a data width of 1 byte, and wherein each of the memory devices has a data width of 4 bits.

20. The memory module of claim 19 , wherein the memory devices are arranged in a pl

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G06F13/1642

  with request queuing · CPC title