Processor and program execution method capable of efficient program execution

Patent metadata

Field	Value
Publication number	US-9823946-B2
Application number	US-201414203569-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Jan 9, 2002
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

First claim

What is claimed is:

1. A processor for executing a plurality of tasks by switching a timeslot and iterating a plurality of timeslots, comprising:
a table in which tasks are defined in correspondence with timeslots, wherein in the table, (i) the number of timeslots to be held in one iteration is defined, (ii) for each of the timeslots a time period of a timeslot in one iteration is designated and, (iii) a task is allotted to a timeslot,
a timeslot is configured to be switched based on the time period which is designated for the timeslot, and configured to be iterated after a defined number of timeslots are switched, and
a task is selected and executed by referring to the table in response to switching of a timeslot,
wherein the tasks include first and second realtime processing tasks and a non-realtime processing task,
a first timeslot to which the first realtime processing task is allotted is configured to exceed the time period designated for the first timeslot,
a second timeslot to which the second realtime processing task is allotted is configured to exceed the time period designated for the second timeslot,
a third timeslot to which the non-realtime processing task is allotted is configured to lose the time period designated for the third timeslot so as to maintain a total time period of the one iteration, and
a duration of the third timeslot is shorten by total amount of excess of the time period of the first timeslot and excess of the time period of the second timeslot.

2. A processing method for executing a plurality of tasks by switching a timeslot and iterating a plurality of timeslots, comprising:
defining the number of timeslots to be held in one iteration,
designating a time period of a timeslot for each of the timeslots in one iteration, and
allotting each of the plurality of tasks to a corresponding timeslot,
(i) switching a timeslot based on the time period which is designated for the timeslot,
(ii) selecting a task which is allotted to a timeslot to be switched to,
(iii) executing the task, and
iterating the steps (i),(ii) and (iii) after the number of timeslots are switched, the number being defined,
wherein the tasks include first and second realtime processing tasks and a non-realtime processing task,
a first timeslot is allotted to the first realtime processing task,
a second timeslot is allotted to the second realtime processing task,
a third timeslot is allotted to the non-realtime processing task,
the first timeslot is terminated after expiration of the time period which is designated for the first timeslot,
the second timeslot is terminated after expiration of the time period which is designated for the second timeslot,
the third timeslot is terminated before expiration of the time period which is designated for the third timeslot so as to maintain a total time period of the one iteration, and
a duration of the third timeslot is shorten by total amount of excess of the time period of the first timeslot and excess of the time period of the second timeslot.

Assignees

• Panasonic Corp
• Socionext Inc

Inventors

• Kurata Kazushi
• Furukawa Kazuya
• Tanaka Tetsuya
• Higaki Nobuo
• Hayashi Kunihiko
• Kadota Hiroshi
• Kiyohara Tokuzo
• Kimura Kozo
• Nishida Hideshi
• Fujii Shigeki
• Sugimura Toshio

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/462

  with multiple register sets · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title