Circuits for efficient detection of vector signaling codes for chip-to-chip communication

Patent metadata

Field	Value
Publication number	US-9819522-B2
Application number	US-201615271065-A
Country	US
Kind code	B2
Filing date	Sep 20, 2016
Priority date	May 20, 2010
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

First claim

What is claimed is:

1. An apparatus comprising:
a termination network configured to receive symbols of a balanced codeword via a multi-wire bus, the termination network comprising a plurality of termination impedances, each termination impedance coupled to a respective wire of the multi-wire bus and configured to receive a corresponding symbol of the balanced codeword, the termination network further comprising a common mode biasing source coupled to the plurality of termination impedances, the common mode biasing source configured to form a set of biased symbols by biasing the received symbols of the balanced codeword;
a first pair of transistors arranged in a differential amplifier configuration, each transistor in the first pair configured to receive corresponding biased symbols of a first pair of the set of biased symbols, the first pair of transistors configured to generate a first difference signal;
a second pair of transistors arranged in a differential amplifier configuration, each transistor in the second pair configured to receive corresponding biased symbols of a second pair of the set of biased symbols, the second pair of transistors configured to generate a second difference signal, the second pair of the set of biased symbols disjoint from the first pair of the set of biased symbols; and
a summation node connected to the first and second differential amplifiers, the summation node configured to receive the first and second difference signals, and to generate a sum-of-differences signal by performing an analog summation of the first and second difference signals, the sum-of-difference signal used in part in identifying an output bit of a set of output bits.

2. The apparatus of claim 1 , wherein the first and second pairs of transistors comprise NMOS transistors.

3. The apparatus of claim 1 , wherein the first and second pairs of transistors comprise PMOS transistors.

4. The apparatus of claim 1 , further comprising a filter capacitor configured to couple the plurality of termination impedances to a system ground.

5. The apparatus of claim 4 , wherein the common mode biasing source is a voltage source coupled to the termination impedances and the filter capacitor, and wherein the symbols of the balanced codeword are received at the termination impedances via blocking capacitors.

6. The apparatus of claim 4 , wherein the common mode biasing source comprises a plurality of current sources, each current source coupled to a respective termination impedance via a corresponding resistor.

7. The apparatus of claim 1 , wherein the received symbols of the balanced codeword sum to zero.

8. The apparatus of claim 7 , wherein each balanced codeword is permutation of [+1, −/13, −1/3, −1/3] or [−1, +1/3, +1/3, +1/3].

9. The apparatus of claim 1 , further comprising a slicer configured to generate the output bit by slicing the sum-of-differences signal.

10. The apparatus of claim 1 , further comprising a decoder, the decoder configured to receive a plurality of sum-of-differences signals and to generate the set of output bits.

11. A method comprising:
receiving symbols of a balanced codeword via a multi-wire bus, each symbol received at a corresponding termination impedance of a plurality of termination impedances, and responsively forming, using a common mode biasing source coupled to the plurality of termination impedances, a set of biased symbols by providing a bias to the received symbols of the balanced codeword;
receiving, at a first pair of transistors arranged in a differential amplifier configuration, corresponding biased symbols of a first pair of the set of biased symbols, and responsively generating a first difference signal;
receiving, at a second pair of transistors arranged in a differential amplifier configuration, corresponding biased symbols of a second pair of the set of biased symbols, and responsively generating a second difference signal, the second pair of the set of biased symbols disjoint from the first pair of the set of biased symbols; and
generating a sum-of-differences signal by performing an analog summation of the first and second difference signals, the sum-of-difference signal used in part in identifying an output bit of a set of output bits.

12. The method of claim 11 , wherein the first and second pairs of transistors comprise NMOS transistors.

13. The method of claim 11 , wherein the first and second pairs of transistors comprise PMOS transistors.

14. The method of claim 11 , wherein the plurality of termination impedances is coupled to a system ground via a filter capacitor.

15. The method of claim 14 , wherein the biasing of the received symbols of the balanced codeword comprises applying a bias voltage using a voltage source coupled to the termination impedances and the filter capacitor, and wherein the symbols of the balanced codeword are received at the termination impedances via blocking capacitors.

16. The method of claim 14 , wherein the biasing of the received symbols of the codeword comprises providing currents to the plurality of termination impedances using a plurality of current sources, each current source coupled to a respective termination impedance via a corresponding resistor.

17. The method of claim 11 , wherein the received symbols of the balanced codeword sum to zero.

18. The method of claim 17 , wherein each balanced codeword is permutation of [+1, −/13, −1/3, −1/3] or [−1, +1/3, +1/3, +1/3].

19. The method of claim 11 , further comprising slicing the sum-of-differences signal to form the output bit.

20. The method of claim 11 , further comprising generating the set of output bits based on a plurality of sum-of-differences signals.

Assignees

• Kandou Labs SA

Inventors

• Ulrich roger
• Hunt Peter

Classifications

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L25/02

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H04L2025/03363

  Multilevel (H04L2025/03369 takes precedence) · CPC title

• H04L25/4917 Primary

  using multilevel codes · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title