Optical receiver

US10601522B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10601522-B2
Application numberUS-201716309410-A
CountryUS
Kind codeB2
Filing dateJun 19, 2017
Priority dateJun 20, 2016
Publication dateMar 24, 2020
Grant dateMar 24, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An optical receiver is configured so as to be as less susceptible to noise as possible even in the case where high noise occurs inside an optical transceiver. The optical receiver includes a connection part that connects two photodiodes (PDs) constituting a dual photodiode and a transimpedance amplifier (TIA), wherein signal lines from the dual photodiode are surrounded by a conductor pattern that is not connected to each of the signal lines for each channel, and the conductor pattern is connected to a ground pattern on the transimpedance amplifier or a power source pattern for the PDs.

First claim

Opening claim text (preview).

The invention claimed is: 1. An optical receiver comprising: a PD chip on which two photodiodes (PDs) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, wherein: the two PDs constituting the dual photodiode are connected with their cathodes facing each other, a connecting point of the cathodes being connected to a PD power source pattern on the TIA chip; from two anodes of the two PDs, two signal lines are drawn out and are inputted into the TIA chip; from the cathode connecting point, the conductor pattern is branched so as to surround the two PDs toward circumferential sides of the PD chip, and the branched patterns are drawn out as two PD power source patterns from positions sandwiching the two signal lines and are connected to the PD power source pattern on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a high frequency with a capacitor on the TIA chip. 2. An optical receiver comprising: a PD chip on which two photodiodes (PDs) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, wherein: the two PDs constituting the dual photodiode are connected with their cathodes facing each other, a connecting point of the cathodes being connected to a PD power source pattern on the TIA chip; from two anodes of the two PDs, two signal lines are drawn out and are inputted into the TIA chip; from the cathode connecting point, the conductor pattern is branched so as to surround the two PDs toward circumferential sides of the PD chip via a capacitor, and the branched patterns are drawn out as two ground patterns from positions sandwiching the two signal lines and are connected to ground patterns on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a high frequency with a capacitor on the TIA chip. 3. An optical receiver comprising: a PD chip on which two photodiodes (PDs) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, and wherein: the two PDs constituting the dual photodiode are arranged with their anodes facing each other, and two signal lines are drawn out from both the anodes and are inputted into the TIA chip; the conductor pattern is connected to cathodes of the two PDs on circumferential sides of the PD chip, which are branched on the respective circumferential sides, are drawn out from positions sandwiching the terminals of the two signal lines, and are connected to the PD power source pattern on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a hi h frequency with a capacitor on the TIA chip. 4. An optical receiver comprising: a PD chip on which two photodiodes (PDs) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, wherein the conductor pattern includes two independent conductor patterns that correspond to the respective two PDs for each channel, the conductor patterns being independently connected to the TIA chip and each being capacitively coupled to a ground pattern within the TIA chip, and wherein: the two PDs constituting the dual photodiode are arranged with their anodes facing each other, and two signal lines are drawn out from both the anodes and are inputted into the TIA chip; the conductor pattern is connected to cathodes of the two PDs on circumferential sides of the PD chip in an alternating-current mode via a capacitor, which are branched on the respective circumferential sides, are drawn out from positions sandwiching the two signal lines, and are respectively connected to two PD power source patterns on the TIA chip; and the two PD power source patterns on the TIA chip are respectively grounded at high frequencies with two capacitors on the TIA chip.

Assignees

Inventors

Classifications

  • H04B10/616Primary

    Details of the electronic signal processing in coherent optical receivers · CPC title

  • Electrical arrangements in the receiver · CPC title

  • Coherent receivers · CPC title

  • Electricity · mapped topic

  • Constructional details of devices covered by this subclass (constructional details of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10601522B2 cover?
An optical receiver is configured so as to be as less susceptible to noise as possible even in the case where high noise occurs inside an optical transceiver. The optical receiver includes a connection part that connects two photodiodes (PDs) constituting a dual photodiode and a transimpedance amplifier (TIA), wherein signal lines from the dual photodiode are surrounded by a conductor pattern t…
Who is the assignee on this patent?
Nippon Telegraph & Telephone
What technology area does this patent fall under?
Primary CPC classification H04B10/616. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 24 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).