Protective device with non-volatile memory miswire circuit

Patent metadata

Field	Value
Publication number	US-9819177-B2
Application number	US-201313834636-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

The present invention is directed to an electrical wiring device that includes a processing circuit is configured to determine the wiring state based on detecting a wiring state parameter at the plurality of line terminals during a predetermined period after the tripped state has been established. The processing circuit is configured to store a wiring state indicator in a wiring state register based on a wiring state determination. The wiring state register being preset to trip the circuit interrupter when the AC power source is applied by an installer to the plurality of line terminals or the plurality of load terminals for the first time.

First claim

What is claimed is:

1. An electrical wiring device for use in an electrical distribution system, the electrical distribution system including a plurality of line conductors coupled to an AC power source and a plurality of load conductors, the device comprising:
a plurality of line terminals and a plurality of load terminals configured to terminate the plurality of line conductors and the plurality of load conductors in a wiring state, the wiring state consisting of a properly wired condition when the plurality of line conductors are terminated to the plurality of line terminals and a miswired condition when the plurality of line conductors are terminated to the plurality of load terminals;
a protective circuit assembly coupled to the plurality of line terminals or the plurality of load terminals, the protective circuit assembly including at least one fault detector configured to generate a fault detection signal based on electrical perturbations propagating on at least one of the plurality of line terminals or at least one of the plurality of load terminals;
a circuit interrupter assembly coupled to the protective circuit assembly, the circuit interrupter assembly including a plurality of interrupting contacts configured to establish continuity between the plurality of line terminals and the plurality of load terminals in a reset state in response to a reset stimulus and establish a discontinuity between the plurality of line terminals and the plurality of load terminals in a tripped state in response to a trip stimulus including the fault detection signal or a miswiring state signal when in the miswired condition; and
a processing circuit configured to determine the wiring state based on detecting a wiring state parameter at the plurality of line terminals during a predetermined period after the tripped state has been established, the wiring state parameter corresponding to a signal characteristic of the AC power source, the processing circuit being configured to store a wiring state indicator in a wiring state register based on a wiring state determination, the wiring state register being preset to trip the circuit interrupter when the AC power source is applied by an installer to the plurality of line terminals or the plurality of load terminals for the first time.

2. The device of claim 1 , wherein the processing circuit is configured to trip the circuit interrupter after the reset stimulus if the wiring state indicator indicates that the AC power source is coupled to the plurality of load terminals.

3. The device of claim 1 , wherein the processing circuit is configured to maintain the reset state after the reset stimulus if the wiring state indicator indicates that the AC power source is coupled to the plurality of line terminals.

4. The device of claim 1 , wherein the processing circuit is configured to preset the wiring state indicator to a miswired indication when the device enters the stream of commerce.

5. The device of claim 4 , wherein the preset miswired indication is changed to a proper wiring state indication if the processing circuit detects the wiring state parameter during the predetermined period.

6. The device of claim 4 , wherein the preset miswired indication is maintained if the processing circuit fails to detect the wiring state parameter during the predetermined period.

7. The device of claim 6 , wherein the processing circuit is configured to read the wiring state register in response to detecting a trip stimulus and provide the miswiring state signal to the circuit interrupter if a miswired indication is stored in the wiring state register.

8. The device of claim 1 , further comprising at least one user-accessible button element configured to apply the reset stimulus and the trip stimulus to the circuit interrupter.

9. The device of claim 8 , wherein the at least one user-accessible button element includes a test button and a reset button, the test button and the reset button being independently operable.

10. The device of claim 8 , wherein the at least one user-accessible button element is coupled to a test circuit configured to generate a simulated fault condition.

11. The device of claim 1 , wherein the wiring state register is implemented by an electronic memory device.

12. The device of claim 1 , wherein the wiring state register is implemented by a capacitor element.

13. The device of claim 1 , wherein the wiring state register and the processing circuit are implemented in a single integrated package.

14. The device of claim 11 , wherein the integrated package includes an integrated circuit form factor.

15. The device of claim 1 , wherein the processing circuit is implemented as an embedded microprocessor or a state machine.

16. The device of claim 1 , wherein the processing circuit is implemented by a signal processor, a RISC processor, a CISC processor, at least one application specific integrated circuit (ASIC), at least one field programmable gate array (FPGA) device, at least one customized integrated circuit, or a combination thereof.

17. The device of claim 1 , further including a ground terminal configured to terminate a ground conductor in the electrical distribution system, wherein the processing circuit is configured to transmit a predetermined signal on the ground terminal from time to time, the processing circuit being configured to monitor a response of the electrical wiring device to the predetermined signal to detect a device wiring condition selected from a group of device wiring conditions including the miswired condition, the properly wired condition, a reverse polarity condition, or an open ground condition.

18. The device of claim 17 , wherein the predetermined signal generates the fault detection signal if the device is improperly wired or the ground conductor is not wired to the ground terminal, the fault detection signal being configured to drive the circuit interrupter into the tripped state.

19. The device of claim 17 , wherein the predetermined signal is configured to drive the circuit interrupter into the tripped state if the device is improperly wired or the ground conductor is not wired to the ground terminal.

20. The device of claim 17 , wherein the predetermined signal generates the fault detection signal if the device is properly wired and the ground conductor is terminated to the ground terminal, the processing circuit being configured to drive the circuit interrupter into the tripped state from the reset state absent the fault detection signal.

21. The device of claim 17 , wherein the predetermined signal is generated at a predetermined time in the AC line cycle so as to generate a fault detection signal occurring late in a positive half cycle of the AC power source or during a negative half cycle of the AC cycle of the AC power source.

22. The device of claim 17 , wherein the predetermined signal is generated in response to a correct polarity condition and is not generated in response to a reverse polarity condition.

23. The device of claim 1 , wherein the processing circuit is configured to perform a device integrity test of the protective circuit assembly from time to time, the processing circuit being configured to generate a device integrity fault signal when the protective circuit assembly fails the device integrity test.

24. The device of claim 23 , further including a test circuit configured to generate a test signal as part of the device integrity test, the test signal being

Assignees

• Pass And Seymour Inc
• Pass & Seymour Inc

Inventors

• Du Hai Hu
• Haines Joshua P
• Mcmahon Michael F

Classifications

• H02H11/002 Primary

  in case of inverted polarity or connection; with switching for obtaining correct connection · CPC title