Deposited material and method of formation

Patent metadata

Field	Value
Publication number	US-9818885-B2
Application number	US-201615382918-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Oct 17, 2011
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

First claim

What is claimed is:

1. A semiconductor device comprising:
an opening through a silicon δ-doping layer, an InAlAs layer, an InP etch stop layer, and a n++ InGaAs layer;
a gate dielectric material within the opening, wherein the gate dielectric material comprises:
a first layer comprising a first material, the first layer comprising a first plurality of monolayers, the first plurality of monolayers having a first density;
a second layer over and in physical contact with the first layer, the second layer comprising the first material, the second layer comprising a second plurality of monolayers, the second plurality of monolayers having a second density less than the first density; and
a third layer over and in physical contact with the second layer, the third layer comprising the first material and comprising a third plurality of monolayers, the third plurality of monolayers having a third density greater than the second density; and

a gate electrode over the gate dielectric material.

2. The semiconductor device of claim 1 , wherein the third density is equal to the first density.

3. The semiconductor device of claim 1 , wherein the first material is hafnium oxide.

4. The semiconductor device of claim 1 , wherein the first material is zirconium oxide.

5. The semiconductor device of claim 1 , further comprising source/drain regions in physical contact with the n++ InGaAs layer.

6. The semiconductor device of claim 5 , wherein the source/drain regions extend further from the silicon δ-doping layer than the gate dielectric material.

7. The semiconductor device of claim 6 , wherein the source/drain regions extend further from the silicon δ-doping layer than the gate electrode.

8. A semiconductor device comprising:
a silicon substrate;
a first buffer layer in physical contact with the silicon substrate;
a second buffer layer in physical contact with the first buffer layer;
a barrier layer in physical contact with the second buffer layer;
a QW channel in physical contact with the barrier layer;
an InP layer in physical contact with the QW channel;
an In 0.52 Al 0.48 As layer in physical contact with the InP layer;
a silicon δ-doping layer in physical contact with the In 0.52 Al 0.48 As layer;
an In 0.52 Al 0.49 As layer in physical contact with the silicon δ-doping layer;
an etch stop layer in physical contact with the In 0.52 Al 0.49 As layer;
an n++ InGaAs layer in physical contact with the etch stop layer;
a source/drain region in physical contact with the N++ InGaAs layer;
a first plurality of monolayers of a first material in physical contact with the n++ InGaAs layer, wherein the first plurality of monolayers has a first density; and
a second plurality of monolayers of the first material in physical contact with the first plurality of monolayers, wherein the second plurality of monolayers has a second density different from the first density.

9. The semiconductor device of claim 8 , wherein the first buffer layer is GaAs.

10. The semiconductor device of claim 9 , wherein the second buffer layer is In 0.52 Al 0.48 As.

11. The semiconductor device of claim 10 , wherein the barrier layer is In 0.52 Al 0.48 As.

12. The semiconductor device of claim 11 , wherein the QW channel is In 0.7 Ga 0.3 As.

13. The semiconductor device of claim 8 , wherein the etch stop layer is InP.

14. The semiconductor device of claim 8 , further comprising an electrode over the second plurality of monolayers.

15. A semiconductor device comprising:
a semiconductor substrate; and
a III-V high-k metal gate structure over the semiconductor substrate, wherein the III-V high-k metal gate structure comprises a dielectric layer, the dielectric layer comprising:
a first layer of a first material, the first layer of the first material comprising a first plurality of monolayers and having a first density;
a second layer of the first material, the second layer of the first material comprising a second plurality of monolayers and having a second density less than the first density; and
a third layer of the first material, the third layer of the first material comprising a third plurality of monolayers and having a third density greater than the second density.

16. The semiconductor device of claim 15 , wherein the III-V high-k metal gate structure further comprises:
a first buffer layer in physical contact with the semiconductor substrate;
a second buffer layer in physical contact with the first buffer layer;
a barrier layer in physical contact with the second buffer layer;
a QW channel in physical contact with the barrier layer;
an InP layer in physical contact with the QW channel;
an In 0.52 Al 0.48 As layer in physical contact with the InP layer;
a silicon δ-doping layer in physical contact with the In 0.52 Al 0.48 As layer;
an In 0.52 Al 0.49 As layer in physical contact with the silicon δ-doping layer;
an etch stop layer in physical contact with the In 0.52 Al 0.49 As layer;
an n++ InGaAs layer in physical contact with the etch stop layer;
a source/drain region in physical contact with the n++ InGaAs layer.

17. The semiconductor device of claim 16 , wherein the first material is zirconium oxide.

18. The semiconductor device of claim 16 , wherein the first material is hafnium oxide.

19. The semiconductor device of claim 16 , wherein the first buffer layer is GaAs.

20. The semiconductor device of claim 19 , wherein the second buffer layer is In 0.52 Al 0.48 As.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yao-Wen
• Tsai Cheng-Yuan
• Lin Hsing-Lien

Classifications

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title