Silicon carbide semiconductor device and method for producing the same

Patent metadata

Field	Value
Publication number	US-9818860-B2
Application number	US-201615365150-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Jun 13, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p + type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p + type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device comprising:
a first or second conductivity type substrate made of silicon carbide;
a drift layer disposed on the substrate, the drift layer made of a first conductivity type silicon carbide having an impurity concentration lower than that of the substrate, the drift layer including a lower layer portion and an upper layer portion, the upper layer portion being disposed above the lower layer portion and having an impurity concentration lower than that of the lower layer portion, each of the upper layer portion and lower layer portion has a uniform dopant concentration;
a base region disposed on the drift layer, the base region made of a second conductivity type silicon carbide;
a source region disposed in an upper layer portion of the base region, the source region made of a first conductivity type silicon carbide having an impurity concentration higher than that of the drift layer;
a first trench that extends from a surface of the source region to a position deeper than the base region, the trench gate structure including a gate insulation film disposed on an inner wall surface of the first trench and a gate electrode disposed on the gate insulation film;
a second conductivity type region disposed in a second trench that extends from the surface of the source region to the drift layer while passing through the base region and is deeper than the first trench, the second conductivity type region including a second conductivity type first low concentration region and a second conductivity type first high concentration region, the first low concentration region having a second conductivity type impurity concentration being set relatively low, the first high concentration region being disposed on a surface of the first low concentration region and having a second conductivity type impurity concentration being set higher than that of the first low concentration region, the first high concentration region being deeper than the first trench to provide a deep layer;
a source electrode electrically connected to the base region through the source region and the second conductivity type region; and
a drain electrode disposed on a rear surface of the substrate, wherein
the silicon carbide semiconductor device is provided with a semiconductor switching element with an inversion type trench gate structure in which an inversion type channel region is formed on a surface portion of the base region located on a side surface of the first trench by controlling an application voltage to the gate electrode to cause an electric current between the source electrode and the drain electrode through the source region and the drift layer, and a super junction structure is provided by alternately arranged P and N columns that are provided by the first low concentration region and a portion of the drift layer opposing to the first low concentration region, and further comprising:
a first conductivity type or I type surrounding region disposed on an inner wall of the second trench,
wherein the first low concentration region and the first high concentration region are disposed on the surrounding region.

2. A method for producing a silicon carbide semiconductor device, comprising:
providing a first or second conductivity type substrate made of silicon carbide;
forming a drift layer on the substrate, the drift layer made of a first conductivity type silicon carbide having an impurity concentration lower than that of the substrate, the drift layer including a lower layer portion and an upper layer portion, the upper layer portion being disposed above the lower layer portion and having an impurity concentration lower than that of the lower layer portion, each of the upper layer portion and lower layer portion has a uniform dopant concentration;
forming a base region on the drift layer, the base region made of a second conductivity type silicon carbide;
forming a source region in an upper layer portion of the base region, the source region made of a first conductivity type silicon carbide having an impurity concentration higher than that of the drift layer;
forming a first trench that extends from a surface of the source region to a position deeper than the base region, the trench gate structure including a gate insulation film disposed on an inner wall surface of the first trench and a gate electrode disposed on the gate insulation film;
forming a second trench that extends from the surface of the source region to the drift layer while passing through the base region and is deeper than the first trench, the second conductivity type region including a second conductivity type first low concentration region and a second conductivity type first high concentration region, the first low concentration region having a second conductivity type impurity concentration being set relatively low, the first high concentration region being disposed on a surface of the first low concentration region and having a second conductivity type impurity concentration being set higher than that of the first low concentration region, the first high concentration region being deeper than the first trench to provide a deep layer, the first low concentration region and the first high concentration region are disposed on the surrounding region;
forming a first conductivity type or I type surrounding region disposed on an inner wall of the second trench;
forming a second conductivity type region in the second trench;
forming a source electrode electrically connected to the base region through the source region and the second conductivity type region; and
forming a drain electrode disposed on a rear surface of the substrate, wherein
the silicon carbide semiconductor device is provided with a semiconductor switching element with an inversion type trench gate structure in which an inversion type channel region is formed on a surface portion of the base region located on a side surface of the first trench by controlling an application voltage to the gate electrode to cause an electric current between the source electrode and the drain electrode through the source region and the drift layer, and a super junction structure is provided by alternately arranged P and N columns that are provided by the first low concentration region and a portion of the drift layer opposing to the first low concentration region.

3. The method for producing the silicon carbide semiconductor device according to claim 2 , wherein
a region where the semiconductor switching element is formed is referred to as a cell region, and
the silicon carbide semiconductor device includes an outer peripheral withstand voltage structure disposed in an outer peripheral region surrounding an outer periphery of the cell region, the method comprising:
forming a third trench in the outer peripheral region simultaneously with the forming of the second trench;
forming the first layer and the second layer in the third trench simultaneously with the forming of the first layer and the second layer in the second trench;
forming a second conductivity type second low concentration region having a second conductivity type impurity concentration equal to that of the first low concentration region and a second conductivity type second high concentration region having a second conductivity type impurity concentration higher than that of the second low concentration region and being deeper than the first trench by the first layer and the second layer left in the third trench, simultaneously with the partly removing of the first layer and the second layer to provide the first low concentration region and the first high concentration region, thereby forming an impurity embedded region; and
forming a recessed portion in a region where the impurity embedded region is to be formed in the outer peripheral

Assignees

• Denso Corp
• Toyota Motor Co Ltd
• Sugimoto Masahiro
• Takaya Hidefumi
• Soeno Akitaka
• Morimoto Jun

Inventors

• Takeuchi Yuichi
• Suzuki Naohiro
• Sugimoto Masahiro
• Takaya Hidefumi
• Soeno Akitaka
• Morimoto Jun
• Soejima Narumasa
• Watanabe Yukihiko

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title