Integrated RF front end system

Patent metadata

Field	Value
Publication number	US-9818821-B2
Application number	US-201615216620-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jun 28, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

First claim

What is claimed is:

1. A semiconductor device for an integrated front-end module comprising:
a high-resistivity bulk silicon substrate having a first impurity type and a top surface that lies in a top plane;
a silicon germanium bipolar transistor disposed above the high-resistivity bulk silicon substrate;
a well located between the silicon germanium bipolar transistor and a passive device, the well providing at least partial electrical isolation between the silicon germanium bipolar transistor and the passive device; and
a trench disposed between a sub-collector region of the silicon germanium bipolar transistor and the well, the trench a distance away from the sub-collector region and configured to impede movement across the trench of carriers in the high-resistivity bulk silicon substrate.

2. The semiconductor device of claim 1 wherein the sub-collector region is of a second impurity type that differs from the first impurity type.

3. The semiconductor device of claim 1 further comprising a low-resistivity epitaxial layer disposed adjacent to the top surface and lying in a plane parallel to the top plane.

4. The semiconductor device of claim 3 wherein a resistivity of the low-resistivity epitaxial layer is within a range of around 1-100 Ohms*cm.

5. The semiconductor device of claim 3 wherein the low-resistivity epitaxial layer is of a second impurity type that differs from the first impurity type.

6. The semiconductor device of claim 1 wherein a resistivity of the high-resistivity bulk silicon substrate is at least approximately 1000 Ohms*cm.

7. The semiconductor device of claim 1 wherein the well has a lower resistivity than a resistivity of the high-resistivity bulk silicon substrate.

8. The semiconductor device of claim 1 wherein the trench is adjacent to the well.

9. The semiconductor device of claim 1 wherein the well substantially surrounds the transistor sub-collector region.

10. The semiconductor device of claim 1 wherein a region positioned between the well and the sub-collector region has a resistivity higher than both the well and the sub-collector region.

11. A wireless device comprising:
a front-end module including a high-resistivity bulk silicon substrate, a silicon germanium bipolar transistor, a well, and a trench, the high-resistivity bulk silicon substrate having a first impurity type and a top surface that lies in a top plane, the silicon germanium bipolar transistor disposed above the high-resistivity bulk silicon substrate, the well located between the silicon germanium bipolar transistor and a passive device, the well providing at least partial electrical isolation between the silicon germanium bipolar transistor and the passive device, and the trench disposed between a sub-collector region of the silicon germanium bipolar transistor and the well, the trench a distance away from the sub-collector region and configured to impede movement across the trench of carriers in the high-resistivity bulk silicon substrate; and
an antenna in electrical communication with the front-end module, the antenna configured to receive and transmit wireless signals.

12. The wireless device of claim 11 wherein the high-resistivity bulk silicon substrate has a resistivity of at least approximately 1000 Ohms*cm.

13. The wireless device of claim 11 wherein the high-resistivity bulk silicon substrate has a resistivity of at least approximately 500 Ohms*cm.

14. The wireless device of claim 11 wherein the sub-collector region is of a second impurity type that differs from the first impurity type.

15. The wireless device of claim 11 wherein the front-end module further includes a low-resistivity epitaxial layer disposed adjacent to the top surface and lying in a plane parallel to the top plane.

16. The wireless device of claim 15 wherein a resistivity of the low-resistivity epitaxial layer is within a range of around 1-100 Ohms*cm.

17. The wireless device of claim 15 wherein the low-resistivity epitaxial layer is of a second impurity type that differs from the first impurity type.

18. The wireless device of claim 11 wherein the well has a lower resistivity than a resistivity of the high-resistivity bulk silicon substrate.

19. The wireless device of claim 11 wherein the first impurity type is p-type.

20. The wireless device of claim 11 wherein the well substantially surrounds the transistor sub-collector region.

21. The wireless device of claim 11 wherein a region positioned between the well and the sub-collector region has resistivity characteristics higher than both the well and the sub-collector region.

22. A method of fabricating a front-end module, the method comprising:
creating a high-resistivity bulk silicon substrate in a silicon wafer;
implanting a low-resistivity implant in particular regions of the silicon wafer;
forming a number of active devices on the high-resistivity bulk silicon substrate;
forming one or more passive devices on the high-resistivity bulk silicon substrate; and
forming an epitaxial layer of low-resistivity silicon on the upper surface of the silicon wafer.

23. The method of claim 22 further comprising destroying at least a portion of the epitaxial layer in particular regions of the silicon wafer to restore high-resistivity characteristics of the high-resistivity bulk silicon substrate in the particular regions.

Assignees

• Skyworks Solutions Inc

Inventors

• Mcpartlin Michael Joseph
• Doherty Mark M

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title