Fabrication method of pixel structure

Patent metadata

Field	Value
Publication number	US-9818774-B2
Application number	US-201514913475-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Mar 2, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A fabrication method of a pixel structure is provided. The fabrication method includes: forming a gate electrode, a gate insulating layer, an active layer, a pixel electrode layer and a source-drain electrode layer on a substrate, and etching the source-drain electrode layer by using a photoresist pattern to form a source electrode and a drain electrode; ashing the photoresist pattern, so as to align edges of the ashed photoresist pattern with edges of the source electrode and the drain electrode; etching a silicon oxide generated in ashing the photoresist pattern; and etching a semiconductor layer between the source electrode and the drain electrode by an etching process to form a channel. The fabrication method can remove indium-containing material remained on both sides of a source electrode and a drain electrode, and can resolve a problem that a width of a channel between the source electrode and the drain electrode is small.

First claim

The invention claimed is:

1. A fabrication method of a pixel structure, comprising:
forming a gate electrode, a gate insulating layer, an active layer, a pixel electrode layer and a source-drain electrode layer on a substrate, and etching the source-drain electrode layer by using a photoresist pattern to form a source electrode and a drain electrode;
ashing both sides of the photoresist pattern, and removing indium-containing material remained on both sides of the source electrode and the drain electrode, so as to align edges of the ashed photoresist pattern with edges of the source electrode and the drain electrode;
etching a silicon oxide generated when ashing the photoresist pattern; and
etching a semiconductor layer between the source electrode and the drain electrode by a dry etching process to form a channel, wherein a width etched of the semiconductor layer is equal to a distance between the source electrode and the drain electrode.

2. The fabrication method of the pixel structure according to claim 1 , wherein the photoresist pattern includes a first photoresist pattern and a second photoresist pattern which are independent of each other, wherein a width of the ashed first photoresist pattern is same as that of the source electrode, so as to align edges of a structure of the ashed first photoresist pattern with edges of the source electrode; and a width of the ashed second photoresist pattern is same as that of the drain electrode, so as to align edges of a structure of the ashed second photoresist pattern with edges of the drain electrode.

3. The fabrication method of the pixel structure according to claim 2 , wherein a time for ashing the first photoresist pattern is determined according to an area of a non-overlapping region between the first photoresist pattern and the source electrode, and a time for ashing the second photoresist pattern is determined according to an area of a non-overlapping region between the second photoresist pattern and the drain electrode.

4. The fabrication method of the pixel structure according to claim 1 , wherein a gas for ashing the photoresist pattern is O 2 , or a mixed gas of O 2 and SF 6 , a source radio frequency power is 1000 W-3000 W, a biased radio frequency power is 500 W-1500 W, and a pressure is 100-300 mtorr.

5. The fabrication method of the pixel structure according to claim 1 , wherein the silicon oxide is generated by oxidizing the semiconductor layer with a gas generated in ashing the photoresist pattern.

6. The fabrication method of the pixel structure according to claim 1 , wherein, for etching the silicon oxide, a source radio frequency power is 2000 W-4000 W, a biased radio frequency power is 2000 W-4000 W, and a pressure is 10-100 mtorr.

7. The fabrication method of the pixel structure according to claim 1 , wherein a width of the silicon oxide etched is equal to a distance between the source electrode and the drain electrode, so as to align edges of a structure of the etched silicon oxide with a lower edge of the source electrode with respect to the drain electrode and a lower edge of the drain electrode with respect to the source electrode, respectively.

8. The fabrication method of the pixel structure according to claim 1 , wherein a gas for etching the semiconductor layer between the source electrode and the drain electrode is a mixed gas of He, Cl 2 and SF 6 , a source radio frequency power is 200 W-1000 W, a biased radio frequency power is 200 W-1000 W, and a pressure is 10-100 mtorr.

9. The fabrication method of the pixel structure according to claim 1 , wherein edges of a structure of the etched semiconductor layer are aligned with a lower edge of the source electrode with respect to the drain electrode and a lower edge of the drain electrode with respect to the source electrode, respectively.

10. The fabrication method of the pixel structure according to claim 1 , further comprising:
removing the photoresist pattern covering the source electrode and the drain electrode.

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Jin Xiaotao
• Chen Zelin
• Ou Fei
• Yang Xiaofeng

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L29/66765

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic