Three-dimensional semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9818758-B2
Application number	US-201615093467-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Nov 5, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.

First claim

What is claimed is:

1. A 3-D semiconductor device, comprising:
a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein,
a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions;
a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines;
a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines;
a bit line connected to a top surface of the first vertical plug; and
a source line connected to a top surface of the second vertical plug,
wherein the first and second vertical plugs include a vertical channel layer and have different sizes.

2. The 3-D semiconductor device of claim 1 , wherein each of the first and second vertical plugs includes a memory layer.

3. The 3-D semiconductor device of claim 2 , wherein the vertical channel layer is formed at the center of each of the first and second vertical plugs, and the memory layer is formed to surround the channel layer.

4. The 3-D semiconductor device of claim 3 , wherein the memory layer includes:
a tunnel insulating layer surroundings the channel layer;
a charge trapping layer surrounding the tunnel insulating layer; and
a blocking layer surrounding the charge trapping layer.

5. The 3-D semiconductor device of claim 1 , wherein the first vertical plug, the pipe transistor, and the second vertical plug constitute a ‘U’-shaped string.

6. The 3-D semiconductor device of claim 1 , wherein the word lines are spaced apart from each other between the first and second vertical plugs.

7. The 3-D semiconductor device of claim 6 , further comprising drain select lines formed between the bit line and the word lines formed along the first vertical plug.

8. The 3-D semiconductor device of claim 6 , further comprising drain select lines formed between the bit line and the word lines formed along the first vertical plug.

9. The 3-D semiconductor device of claim 1 , wherein, if the first vertical plug has a weaker program disturbance or a slower program or erase operation speed than the second vertical plug, the width of the first vertical plug is formed narrower than the width of the second vertical plug, and
wherein, if the second vertical plug has a weaker program disturbance or a program or erase operation speed slower than the first vertical plug, the width of the second vertical plug is formed narrower than the width of the first vertical plug.

10. The 3-D semiconductor device of claim 9 , wherein the width of a vertical plug having a wider width among the first and second vertical plugs is narrower than a length of a minor axis of the pipe transistor.

11. The 3-D semiconductor device of claim 10 , wherein a major axis of the pipe transistor extends in a direction parallel to the word lines.

12. The 3-D semiconductor device of claim 10 , wherein a major axis of the pipe transistor extends in a direction intersecting the word lines.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L23/535

  Electricity · mapped topic

• H01L21/76897

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic