Method of improving bipolar device signal to noise performance by reducing the effect of oxide interface trapping centers

Patent metadata

Field	Value
Publication number	US-9818740-B2
Application number	US-201615368958-A
Country	US
Kind code	B2
Filing date	Dec 5, 2016
Priority date	Nov 16, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate comprising a silicon-based semiconductor material extending to a top surface of the substrate;
an n-channel metal oxide semiconductor (NMOS) transistor;
a p-channel metal oxide semiconductor (PMOS) transistor; and
a vertical bipolar transistor comprising:
an emitter of a first conductivity type disposed in the substrate, the emitter extending to a top surface of the substrate;
an intrinsic base of a second, opposite, conductivity type, disposed in the substrate below, and laterally surrounding the emitter, the intrinsic base contacting the emitter at an emitter-base junction, the intrinsic base extending to the top surface of the substrate adjacent to the emitter under a gate dielectric layer at the top surface, there being a gate over the gate dielectric layer, the gate surrounding the emitter and being substantially aligned to the emitter;
an extrinsic base of the second conductivity type laterally surrounding and contacting the intrinsic base, the extrinsic base having a net average dopant density at least 3 times a net average dopant density of the intrinsic base, the gate extending past the intrinsic base and partway over the extrinsic base; and
a collector of the first conductivity type disposed in the substrate below the intrinsic base, the collector contacting the intrinsic base at a base-collector junction.

2. The integrated circuit of claim 1 , wherein:
the extrinsic base comprises a well of the second conductivity type; and
the intrinsic base comprises a portion of the well of the second conductivity type that is counterdoped with dopants of the first conductivity type.

3. The integrated circuit of claim 2 , wherein:
the well of the second conductivity type has a similar distribution of dopants of the second conductivity type as a well containing one of the NMOS transistor and the PMOS transistor.

4. The integrated circuit of claim 1 , wherein:
the intrinsic base is 200 nanometers to 400 nanometers thick between the emitter-base junction and the base-collector junction; and
the average net dopant density in the intrinsic base is 1×10 17 cm −3 to 5×10 17 cm −3 .

5. The integrated circuit of claim 1 , wherein the intrinsic base extends at least 500 nanometers under the gate.

6. The integrated circuit of claim 1 , wherein the emitter is electrically coupled to the gate.

7. The integrated circuit of claim 1 , wherein the top surface of the substrate in the emitter is substantially covered with metal silicide.

8. The integrated circuit of claim 1 , wherein metal silicide is disposed on the top surface of the substrate in the emitter, there being a portion of the top surface in the emitter adjacent to the gate which is free of the metal silicide.

9. The integrated circuit of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

10. An integrated circuit, comprising:
a substrate comprising a silicon-based semiconductor material;
an NMOS transistor;
a PMOS transistor; and
a vertical bipolar transistor, comprising:
an emitter of a first conductivity type disposed in the substrate;
an intrinsic base of a second, opposite, conductivity type disposed in the substrate, at least a portion of the intrinsic base being under the emitter, the intrinsic base contacting the emitter at an emitter-base junction; and
a collector of the first conductivity type disposed in the substrate, at least a portion of the collector being under the intrinsic base, the collector contacting the intrinsic base at a base-collector junction, the intrinsic base being configured to have a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at the emitter-base junction, and except at the base-collector junction.

11. The integrated circuit of claim 10 , the vertical bipolar transistor comprising an extrinsic base contacting and surrounding the intrinsic base, the extrinsic base having a net average dopant density at least 3 times the net average dopant density of the intrinsic base, which provides band bending to provide at least a portion of the band barrier where the extrinsic base contacts the intrinsic base.

12. The integrated circuit of claim 10 , the intrinsic base extending to a top surface of the substrate adjacent to the emitter under a gate dielectric layer at the top surface, there being a gate over the gate dielectric layer, the gate being configured to accumulate the intrinsic base under the gate dielectric layer to provide an accumulated layer which provides band bending to provide at least a portion of the band barrier where the intrinsic base extends to the top surface.

13. An integrated circuit, comprising:
an n-channel metal oxide semiconductor (NMOS) transistor;
a p-channel metal oxide semiconductor (PMOS) transistor; and
a vertical bipolar transistor comprising:
an emitter of a first conductivity type disposed in a substrate, the emitter extending to a top surface of the substrate;
an intrinsic base of a second, opposite, conductivity type, disposed in the substrate below, and laterally surrounding the emitter, the intrinsic base contacting the emitter at an emitter-base junction, the intrinsic base extending to the top surface of the substrate adjacent to the emitter under a gate dielectric layer at the top surface, there being a gate over the gate dielectric layer, the gate surrounding the emitter and being substantially aligned to the emitter;
an extrinsic base of the second conductivity type laterally surrounding and contacting the intrinsic base, the gate extending past the intrinsic base and partway over the extrinsic base; and
a collector of the first conductivity type disposed in the substrate below the intrinsic base, the collector contacting the intrinsic base at a base-collector junction.

14. The integrated circuit of claim 13 , wherein:
the intrinsic base is 200 nanometers to 400 nanometers thick between the emitter-base junction and the base-collector junction; and
the average net dopant density in the intrinsic base is 1×10 17 cm −3 to 5×10 17 cm −3 .

15. The integrated circuit of claim 13 , wherein the intrinsic base extends at least 500 nanometers under the gate.

16. The integrated circuit of claim 13 , wherein the top surface of the substrate in the emitter is substantially covered with metal silicide.

17. The integrated circuit of claim 13 , wherein metal silicide is disposed on the top surface of the substrate in the emitter, there being a portion of the top surface in the emitter adjacent to the gate which is free of the metal silicide.

18. The integrated circuit of claim 13 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

Assignees

• Texas Instruments Inc

Inventors

• Tian Weidong
• Wang Yuguo
• Chatterjee Tathagata
• Aggarwal Rajni J

Classifications

• H01L29/7395

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic

• H01L29/1004

  Electricity · mapped topic

• H01L29/0688

  Electricity · mapped topic

• H01L27/0623 Primary

  Electricity · mapped topic