Carrier structure, packaging substrate, electronic package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9818635-B2
Application number	US-201514982142-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jul 31, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

First claim

What is claimed is:

1. An electronic package, comprising:
a circuit structure having a first surface and a second surface opposite to the first surface, wherein a first circuit layer is formed on the first surface of the circuit structure and a second circuit layer is formed on the second surface of the circuit structure, the first circuit layer having a minimum trace width less than that of the second circuit layer, and wherein the minimum trace width of the first circuit layer is 0.7 to 5 μm, and the minimum trace width of the second circuit layer is 5 to 10 μm;
a separation layer formed on the first surface of the circuit structure;
a metal layer formed on the separation layer and electrically connected to the first circuit layer;
an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and
an encapsulant formed on the circuit structure to encapsulate the electronic element.

2. The package of claim 1 , wherein the separation layer is a thermal SiO 2 layer or an adhesive layer.

3. The package of claim 1 , wherein the metal layer is a patterned circuit layer.

4. The package of claim 1 , further comprising at least an assisting layer formed on the separation layer in a manner that the metal layer is formed on the assisting layer.

5. The package of claim 1 , further comprising a plurality of conductive elements formed on the second surface of the circuit structure.

6. A carrier structure, comprising:
a carrier;
a separation layer bonded to the carrier; and
a circuit structure having a first surface bonded to the separation layer and a second surface opposite to the first surface, wherein a first circuit layer is formed on the first surface of the circuit structure and a second circuit layer is formed on the second surface of the circuit structure, the first circuit layer having a minimum trace width less than that of the second circuit layer, and wherein the minimum trace width of the first circuit layer is 0.7 to 5 μm, and the minimum trace width of the second circuit layer is 5 to 10 μm.

7. The structure of claim 6 , wherein the separation layer is a thermal SiO2 layer or an adhesive layer.

8. A packaging substrate, comprising:
a circuit structure having a first surface and a second surface opposite to the first surface, wherein a first circuit layer is formed on the first surface of the circuit structure and a second circuit layer is formed on the second surface of the circuit structure, the first circuit layer having a minimum trace width less than that of the second circuit layer, and wherein the minimum trace width of the first circuit layer is 0.7 to 5 μm, and the minimum trace width of the second circuit layer is 5 to 10 μm;
a separation layer formed on the first surface of the circuit structure; and
a metal layer formed on the separation layer and electrically connected to the first circuit layer.

9. The substrate of claim 8 , wherein the separation layer is a thermal SiO 2 layer or an adhesive layer.

10. The substrate of claim 8 , wherein the metal layer is a patterned circuit layer.

11. The substrate of claim 8 , further comprising at least an assisting layer formed on the separation layer in a manner that the metal layer is formed on the assisting layer.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Lu Chang-Lun

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07507

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title