Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Patent metadata

Field	Value
Publication number	US-9818058-B2
Application number	US-201615154169-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Dec 21, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

First claim

What is claimed is:

1. A method, comprising:
maintaining neuron information for multiple neurons of a neural network;
maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and
based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network;
wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed.

2. The method of claim 1 , wherein:
each processor multiplexes computation and control logic for a set of neurons of the neural network;
each time step is divided into multiple time slots, the total number of time slots based on the number of neurons each processor multiplexes computation and control logic for;
each time slot corresponds to an axon of the neural network, and, in the time slot, one or more incoming firing events targeting the corresponding axon are integrated; and
for each neuron, the neuron information includes a membrane potential variable of the neuron and a threshold parameter for the neuron.

3. The method of claim 2 , further comprising:
for each neuron, generating an outgoing firing event in response to a membrane potential variable of the neuron exceeding a threshold parameter for the neuron.

4. The method of claim 1 , further comprising:
updating the neuron information based on the integrated incoming firing events.

5. The method of claim 1 , further comprising:
maintaining routing information for the multiple neurons.

6. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:
maintaining neuron information for multiple neurons of a neural network;
maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and
based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network;
wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed.

7. The system of claim 6 , wherein:
each processor multiplexes computation and control logic for a set of neurons of the neural network;
each time step is divided into multiple time slots, the total number of time slots based on the number of neurons each processor multiplexes computation and control logic for;
each time slot corresponds to an axon of the neural network, and, in the time slot, one or more incoming firing events targeting the corresponding axon are integrated; and
for each neuron, the neuron information includes a membrane potential variable of the neuron and a threshold parameter for the neuron.

8. The system of claim 7 , the method further comprising:
for each neuron, generating an outgoing firing event in response to a membrane potential variable of the neuron exceeding a threshold parameter for the neuron.

9. The system of claim 6 , the method further comprising:
updating the neuron information based on the integrated incoming firing events.

10. The system of claim 6 , the method further comprising:
maintaining routing information for the multiple neurons.

11. A non-transitory computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:
maintaining neuron information for multiple neurons of a neural network;
maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and
based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network;
wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed.

12. The computer program product of claim 11 , wherein:
each processor multiplexes computation and control logic for a set of neurons of the neural network;
each time step is divided into multiple time slots, the total number of time slots based on the number of neurons each processor multiplexes computation and control logic for;
each time slot corresponds to an axon of the neural network, and, in the time slot, one or more incoming firing events targeting the corresponding axon are integrated; and
for each neuron, the neuron information includes a membrane potential variable of the neuron and a threshold parameter for the neuron.

13. The computer program product of claim 12 , the method further comprising:
for each neuron, generating an outgoing firing event in response to a membrane potential variable of the neuron exceeding a threshold parameter for the neuron.

14. The computer program product of claim 11 , the method further comprising:
updating the neuron information based on the integrated incoming firing events.

15. The computer program product of claim 11 , the method further comprising:
maintaining routing information for the multiple neurons.

Assignees

• IBM

Inventors

• Arthur John V
• Brezzo Bernard V
• Chang Leland
• Friedman Daniel J
• Merolla Paul A
• Modha Dharmendra S
• Montoye Robert K
• Seo Jae-Sun
• Tierno Jose A

Classifications

• G06N3/08

  Learning methods · CPC title

• G06N3/04 Primary

  Architecture, e.g. interconnection topology · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title