Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region

Patent metadata

Field	Value
Publication number	US-9817644-B2
Application number	US-201514867950-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Sep 25, 2010
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

First claim

What is claimed is:

1. A computing device to optimize program code, the computing device comprising:
a compiler hardware module to: (i) identify a section of program code to be optimized, (ii) demarcate at least a portion of the section of program code as an atomic region in response to identification of the section of program code to be optimized, (iii) insert conditional commit code at a conditional commit point determined to be within the atomic region, and (iv) optimize the section of program code in response to identification of the section of program code to be optimized; and
a decode hardware module to decode the conditional commit code within the atomic region.

2. The computing device of claim 1 , wherein to demarcate at least a portion of the section of program code as an atomic region comprises to: (i) insert a start transaction instruction at a beginning of the portion of the section of code, and (ii) insert an end transaction instruction at an end of the portion of the section of code.

3. The computing device of claim 1 , wherein to insert the conditional commit code at the conditional commit point determined to be within the atomic region comprises to insert a conditional commit code to:
determine a representation of an availability of hardware resources adapted to support transactional execution; and
commit the atomic region before an end of the atomic region in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

4. The computing device of claim 3 , wherein the conditional commit code is to jump to a branch target address in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

5. The computing device of claim 4 , wherein the conditional commit code comprises a conditional commit instruction, and wherein the conditional commit instruction comprises the branch target address.

6. The computing device of claim 4 , wherein the compiler hardware module is further to insert a commit instruction at the branch target address, wherein the commit instruction is to commit the atomic region.

7. The computing device of claim 1 , wherein to optimize the section of program code comprises to optimize the section of code via an optimization technique selected from a group consisting of Partial Redundancy Load Elimination (PRLE), Partial Dead Store Elimination (PDSE), loop optimization, data-flow optimization, code generation optimization, bounds checking elimination, branch offset optimization, dead code elimination, and jump threading.

8. A non-transitory, machine readable medium comprising a plurality of instructions stored thereon that in response to being executed by a computing device, cause the computing device to:
identify a section of program code to be optimized;
demarcate at least a portion of the section of program code as an atomic region in response to identification of the section of program code to be optimized;
insert conditional commit code at a conditional commit point determined to be within the atomic region; and
optimize the section of program code in response to identification of the section of program code to be optimized.

9. The non-transitory, machine readable medium of claim 8 , wherein to demarcate at least a portion of the section of program code as an atomic region comprises to: (i) insert a start transaction instruction at a beginning of the portion of the section of code, and (ii) insert an end transaction instruction at an end of the portion of the section of code.

10. The non-transitory, machine readable medium of claim 8 , wherein to insert the conditional commit code at the conditional commit point determined to be within the atomic region comprises to insert a conditional commit code to:
determine a representation of an availability of hardware resources adapted to support transactional execution; and
commit the atomic region before an end of the atomic region in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

11. The non-transitory, machine readable medium of claim 10 , wherein the conditional commit code is to jump to a branch target address in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

12. The non-transitory, machine readable medium of claim 11 , wherein the conditional commit code comprises a conditional commit instruction, and wherein the conditional commit instruction comprises the branch target address.

13. The non-transitory, machine readable medium of claim 11 , further comprising a plurality of instructions stored thereon that in response to being executed by the computing device, cause the computing device to insert a commit instruction at the branch target address, wherein the commit instruction is to commit the atomic region.

14. The non-transitory, machine readable medium of claim 8 , wherein to optimize the section of program code comprises to optimize the section of code via an optimization technique selected from a group consisting of Partial Redundancy Load Elimination (PRLE), Partial Dead Store Elimination (PDSE), loop optimization, data-flow optimization, code generation optimization, bounds checking elimination, branch offset optimization, dead code elimination, and jump threading.

15. A method for optimizing program code, the method comprising:
identifying, by a computing device, a section of program code to be optimized;
demarcating, by the computing device, at least a portion of the section of program code as an atomic region in response to identifying the section of program code to be optimized;
inserting, by the computing device, conditional commit code at a conditional commit point determined to be within the atomic region; and
optimizing, by the computing device, the section of program code in response to identifying the section of program code to be optimized.

16. The method of claim 15 , wherein demarcating at least a portion of the section of program code as an atomic region comprises: (i) inserting a start transaction instruction at a beginning of the portion of the section of code, and (ii) inserting an end transaction instruction at an end of the portion of the section of code.

17. The method of claim 15 , wherein inserting the conditional commit code at the conditional commit point determined to be within the atomic region comprises inserting a conditional commit code to:
determine a representation of an availability of hardware resources adapted to support transactional execution; and
commit the atomic region before an end of the atomic region in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

18. The method of claim 17 , wherein the conditional commit code is to jump to a branch target address in response to the representation of the availability of the hardware resources indicating insufficient resources to complete execution of the atomic region.

19. The method of claim 18 , further comprising inserting, by the computing device, a commit instruction at the branch target address, wherein the commit instruction is to commit the atomic region.

20. The method of claim 15 , wherein optimizing the section of program code co

Assignees

• Intel Corp

Inventors

• Breternitz Jr Mauricio
• Wu Youfeng
• Wang Cheng
• Borin Edson
• Hu Shiliang
• Zilles Craig B

Classifications

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F11/3688

  for test execution, e.g. scheduling of test suites · CPC title

• G06F11/3672

  Test management · CPC title

• G06F8/52

  Binary to binary · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title