Secure migratable architecture having improved performance features

Patent metadata

Field	Value
Publication number	US-9817580-B2
Application number	US-201615048214-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Jun 30, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Methods and systems for implementing a secure migratable architecture having improved performance features over existing virtualization systems are disclosed. One method includes allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method includes associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process, and receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor of the area descriptors, the request being associated with a plurality of memory addresses within the first memory area. The method includes, in response to the request, performing a check on a tag associated with the first memory area and stored in the first area descriptor. The method further includes, upon completion of the check, storing the data within the first memory area without performing a separate tag check for each of the plurality of memory addresses within the first memory area.

First claim

The invention claimed is:

1. A computing system comprising:
a programmable circuit configured to execute instructions according to a first computing architecture;
a memory communicatively connected to the programmable circuit, the memory storing software executable by the programmable circuit, the software including:
an operating system; and
a process including a firmware environment representing a virtual computing system having a second computing architecture different from the first computing architecture and one or more workloads to be executed within the process,

the software executable to perform a method including:
allocating a portion of the memory for use by the process;
associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process;
receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor, including a common tag value associated with all memory locations within the first memory area, the request being associated with a plurality of memory addresses within the first memory area;
in response to the request, performing a check on a tag associated with the first memory area and stored in the area descriptor; and
upon completion of the check, storing the data within the memory area without performing a separate tag check for each of the plurality of memory addresses within the first memory area;

wherein each of the area descriptors includes a token defining to the firmware environment a base address at which the corresponding memory area is located, the base address translated to an address in the memory managed by the operating system.

2. The system of claim 1 , wherein the portion of the memory is, according to the second architecture implemented in the firmware environment, addressable as contiguous memory.

3. The system of claim 1 , further comprising:
receiving a request to perform an I/O operation associated with a plurality of memory addresses in the first memory area; and
in response to the request, performing a check on the tag associated with the first memory area and stored in the area descriptor; and
upon completion of the check, performing the I/O operation within the memory area without performing a separate tag check for each of the plurality of memory addresses within the first memory area.

4. The system of claim 3 , further comprising an I/O processor, wherein the first memory area is exposed to the I/O processor and includes an I/O control buffer and an I/O data buffer.

5. The system of claim 1 , wherein the first area descriptor defines a type and width of data in the first memory area.

6. The system of claim 1 , wherein the programmable circuit includes circuitry configured to perform a plurality of native arithmetic operations within the first computing architecture, and wherein the second computing architecture uses a common numerical format with the first computing architecture to allow for use of the native arithmetic operations of the programmable circuit during execution of arithmetic operations performed within the firmware environment.

7. The system of claim 1 , wherein storing the data within the memory area includes storing a plurality of data words in contiguous memory within the data area.

8. A computer-implemented method comprising: allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed; associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process; receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor including a common tag value associated with all memory locations within the first memory area, the request being associated with a plurality of memory addresses within the first memory area; in response to the request, performing a check on a tag associated with the first memory area and stored in the first area descriptor; and upon completion of the check, storing the data within the first memory area without performing a separate tag check for each of the plurality of memory addresses within the first memory area
wherein each of the area descriptors includes a token defining to the firmware environment a base address at which the corresponding memory area is located, the base address translated to an address in the memory managed by the operating system.

9. The method of claim 8 , wherein storing the data within the first memory area includes storing a plurality of data words in contiguous memory within the first memory area.

10. The method of claim 8 , further comprising:
receiving a request to perform an I/O operation associated with a plurality of memory addresses in the first memory area; and
in response to the request, performing a check on the tag associated with the first memory area and stored in the area descriptor; and
upon completion of the check, performing the I/O operation within the memory area without performing a separate tag check for each of the plurality of memory addresses within the first memory area.

11. The method of claim 10 , wherein performing the I/O operation within the memory area includes storing a plurality of data words into contiguous memory locations of an I/O data buffer included in the memory area.

12. The method of claim 8 , further comprising:
receiving a second request within the firmware environment to store data within a second memory area of the plurality of memory areas, the second memory area defined by a second area descriptor of the area descriptors, the second request being associated with a second plurality of memory addresses within the second memory area;
in response to the request, performing a check on a plurality of tags stored in a tag memory area separate from but associated with the second memory area, wherein a location of the tag memory area and a location of the second memory area are both stored in a second area descriptor; and
storing the data within the second memory area.

13. The method of claim 12 , further comprising performing a check against each of the plurality of tags associated with the second plurality of memory addresses.

14. The method of claim 13 , wherein storing the data within the second memory area includes storing a plurality of data words in contiguous memory within the second memory area.

15. The method of claim 14 , further comprising updating each of plurality of tags associated with the second plurality of memory addresses.

16. A non-transitory computer-readable storage medium comprising computer-executable instructions stored thereon which, when executed by a computing system, cause the computing system to perform a method comprising: allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed; associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process; receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the firs

Assignees

• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• H04L41/0843

  based on generic templates · CPC title

• G06F3/0617

  in relation to availability · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title