Digital power estimator to control processor power consumption

Patent metadata

Field	Value
Publication number	US-9817469-B2
Application number	US-201514918781-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Jun 21, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

In an embodiment, a digital power estimator (DPE) may be provided that may monitor the processors to estimate the amount of power being consumed. If the estimate exceeds a power threshold, the DPE may throttle one or more of the processors. Additionally, throttling events may be monitored to determine if a change in the operating point is desired. In one embodiment, the DPE throttling events may be counted, and if the counts exceed a count threshold, a change in the operating point to a reduced operation point may be requested. Additionally, if the DPE estimate is below the power threshold (or a second power threshold), a second count of events may be maintained. If the second count exceeds a threshold and the operating point is the reduced operating point, a return to the original operating point may be requested.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of processors;
a digital power estimator (DPE) circuit coupled to the plurality of processors,
wherein the DPE circuit is configured to:
monitor activity in the processors;
estimate an amount of power consumed by the plurality of processors responsive to the activity;
compare the estimated amount of power to a threshold; and
throttle one or more active processors of the plurality of processors responsive to the estimated amount exceeding the threshold, wherein the throttling limits the active processors execution of instructions while permitting instruction execution to continue in the throttled active processors; and

an enable control circuit coupled to the DPE circuit, wherein the enable control circuit is configured to disable the DPE circuit responsive to a maximum potential power consumption of the active processors not exceeding a capability of a power management unit, and wherein the DPE circuit, when disabled, does not monitor the activity in the processors and does not estimate the amount of power consumed by the plurality of processors.

2. The apparatus as recited in claim 1 further comprising a hysteresis counter coupled to the DPE circuit, and wherein the DPE circuit is configured to:
cause the hysteresis counter to increment a first count responsive to detecting that the estimated amount exceeds the threshold; and
generate a request to reduce an operating point of the plurality of processors responsive to the first count.

3. The apparatus as recited in claim 2 wherein the DPE circuit is further configured to:
detect that the estimated amount is less than a second threshold;
cause the hysteresis counter to increment a second count responsive to detecting that the estimated amount is less than the second threshold; and
generate a request to restore the operating point of the plurality of processors responsive to the second count.

4. The apparatus as recited in claim 3 wherein the hysteresis counter is configured to detect that the second count exceeds a count threshold, and wherein the DPE circuit is configured to generate the request to restore the operating point responsive to the second count exceeding the count threshold.

5. The apparatus as recited in claim 4 wherein the hysteresis counter is configured to detect that the first count exceeds the count threshold, and wherein the DPE circuit is configured to generate the request to reduce the operating point responsive to the first count exceeding the count threshold.

6. The apparatus as recited in claim 3 wherein the DPE circuit is further configured to:
cause the second count to be cleared responsive to detecting that the estimated amount exceeds the threshold; and
cause the first count to be cleared responsive to detecting that the estimated amount is less than the second threshold.

7. A method comprising:
setting an operating point for a plurality of active processors, wherein the operating point is set based on a first power consumption of the plurality of active processors when executing a first workload, wherein the first power consumption is less than a maximum power consumption in the plurality of active processors, wherein the maximum power consumption at the operating point exceeds a capability of a power management unit that supplies power to the plurality of active processors;
executing a second workload by the plurality of active processors at the operating point;
estimating a power consumption in the plurality of active processors during execution of the second workload, the estimating implemented by a digital power estimator (DPE) circuit;
detecting, by the DPE circuit, that the estimated power consumption is greater than a second power consumption; and
throttling the plurality of active processors responsive to the detecting.

8. The method as recited in claim 7 wherein the throttling reduces an effective rate of instruction execution but continues to permit some instruction execution.

9. The method as recited in claim 8 wherein the throttling reduces a rate of instruction execution for a subset of instructions that consume more power during execution than other instructions.

10. The method as recited in claim 7 further comprising:
incrementing a first counter responsive to the estimated power consumption exceeding the second power consumption; and
generating a request to reduce an operating point of the plurality of active processors responsive to the first count.

11. The method as recited in claim 10 further comprising:
programming a second threshold of the estimated power consumption;
incrementing a second counter responsive to the estimated power consumption being below the second threshold; and
generating a request to return the operating point of the plurality of active processors to a previous level subsequent to reducing the operating point responsive to the second counter.

12. The method as recited in claim 7 further comprising:
detecting a request to change the operating point to a different operating point;
determining that the maximum power consumed by the plurality of active processors at the different operating point will not exceed the capability of the power management unit; and
disabling the DPE circuit responsive to determining that the maximum power consumed by the plurality of active processors at the different operating point will not exceed the capability.

13. A system comprising:
a power management unit configured to supply a plurality of voltages to a system on a chip (SOC), wherein a first voltage of the plurality of voltages supplies a processor complex in the SOC; and
the SOC coupled to the power management unit, wherein the processor complex includes a plurality of processors and a digital power estimator (DPE) circuit coupled to the plurality of processors, wherein the DPE circuit is configured to:
estimate an amount of power consumed by the plurality of processors; and
responsive to detecting that the estimated amount exceeds a threshold amount that depends on a voltage magnitude for the first voltage and an operating frequency for the processor complex, throttle one or more active processors of the plurality of processors; and

wherein the SOC is configured to:
determine that a maximum potential power consumption of the plurality of processors at the voltage magnitude and operating frequency is less than a maximum amount of power that the power management unit is capable of providing to the SOC via the first voltage; and
disable the DPE circuit, wherein the DPE circuit, when disabled, does not estimate the amount of power consumed by the plurality of processors.

14. The system as recited in claim 13 wherein the SOC is further configured to request a reduced voltage magnitude and a reduced operating frequency for the processor complex responsive to the estimated amount exceeding the threshold amount.

15. The system as recited in claim 14 wherein the SOC is configured to request the reduced voltage magnitude and the reduced operating frequency responsive to the DPE circuit detecting that the estimated amount exceeds the threshold amount a first configurable number of times.

16. The system as recited in claim 15 wherein the SOC is configured to request a return to the voltage magnitude and the operating frequency in effect prior to the reduced voltage magnitude and the reduced operating frequency responsive to the DPE circuit detecting that the estimated amount does not exceed a second threshold amount a second configurable number of times.

17. The s

Assignees

• Apple Inc

Inventors

• Lee Jong-Suk

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic