Selectable and hierarchical power management
US-2024385668-A1 · Nov 21, 2024 · US
Dynamic voltage and frequency management based on active processors
US9304573B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9304573-B2 |
| Application number | US-201313924164-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 21, 2013 |
| Priority date | Jun 21, 2013 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
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In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: a plurality of processors; a power control circuit coupled to the plurality of processors, wherein the power control unit is programmable with data describing a plurality of operating points for the plurality of processors, and wherein the data further includes an indication for each respective operating point of the plurality of operating points indicating a limit to a first number of active processors in the plurality of processo…
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Physics · mapped topic
- G06F1/324Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9304573B2 cover?
- In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processor…
- Who is the assignee on this patent?
- Apple Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F1/324. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).