Embedded buffer circuit compensation scheme for integrated circuits

Patent metadata

Field	Value
Publication number	US-9813046-B2
Application number	US-201615087250-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

First claim

What is claimed is:

1. An apparatus comprising:
a package substrate including conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate, and
a die including buffer circuits and a calibration module coupled to the buffer circuits and the resistor, the buffer circuits including output nodes coupled to the conductive contacts through the conductive paths, the calibration module configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

2. The apparatus of claim 1 , wherein the calibration module is configured to increase a resistance of a selected buffer circuit among the buffer circuits if the voltage at the terminal of the resistor has a value greater than an expected voltage value.

3. The apparatus of claim 1 , wherein the calibration module is configured to decrease a resistance of a selected buffer circuit among the buffer circuits if the voltage at the terminal of the resistor has a value less than an expected voltage value.

4. The apparatus of claim 1 , wherein the calibration module is configured to adjust a resistance of a selected buffer circuit among the buffer circuits until a first value of the voltage at the terminal of the resistor reaches an expected voltage value.

5. The apparatus of claim 4 , wherein the calibration module is configured to adjust a resistance of an additional selected buffer circuit among the buffer circuits until a second value of the voltage at the terminal of the resistor reaches another expected voltage value.

6. The apparatus of claim 1 , wherein the buffer circuits include a first buffer circuit and a second buffer circuit, and the calibration module is configured to adjust a resistance value of the first buffer circuit based on a first target resistance value, and adjust a resistance value of the second buffer circuit based on a second target resistance value.

7. The apparatus of claim 1 , wherein the calibration module is configured to store a table having values corresponding to different expected values of the voltage at the terminal of the resistor during the calibration operation.

8. The apparatus of claim 1 , wherein each of the buffer circuits includes a transistor coupled between a supply node and a respective output node among the output nodes of the buffer circuits, and the calibration module is configured to place the transistor in series with the resistor between the supply node and a ground connection during the calibration operation.

9. The apparatus of claim 1 , wherein the conductive contacts are arranged to couple to a circuit board through either solder balls or conductive pins.

10. An apparatus comprising:
a package substrate including conductive contacts located at a first side of the package substrate, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate, the resistor including a first terminal coupled to a ground connection of the package substrate; and
a die located at a second side of the package substrate opposite from the first side, the die including buffer circuits and a multiplexor circuit, the buffer circuits including output nodes coupled to a portion of the conductive contacts through a portion of the conductive paths, the multiplexor circuit including first nodes respectively coupled to respective output nodes of the buffer circuits, and a second node coupled to a second terminal of the resistor.

11. The apparatus of claim 10 , wherein each of the buffer circuits includes a first transistor coupled between a supply node and a respective output node among the output nodes of the buffer circuits, and a second transistor coupled between the respective output node and a second supply node.

12. The apparatus of claim 10 , wherein the die includes a conductive bump, and the multiplexor circuit is coupled to the second terminal of the resistor through the conductive bump.

13. The apparatus of claim 10 , wherein the buffer circuits include a first buffer circuit and a second buffer circuit, the first buffer circuit arranged to have a first target resistance value, and the second buffer circuit arranged to have a second target resistance value.

14. The apparatus of claim 10 , wherein the die includes a calibration module, and the calibration module includes a filter coupled to the second terminal of the resistor.

15. The apparatus of claim 10 , further comprising an additional die located at the second side of the package substrate and coupled to the second terminal of the resistor.

16. The apparatus of claim 15 , wherein the additional die includes additional buffer circuits and an additional multiplexor circuit, the additional buffer circuits including output nodes coupled to the conductive contacts of the package substrate, the additional multiplexor circuit including first nodes coupled to respective output nodes of the additional buffer circuits, and a second node coupled to the second terminal of the resistor.

17. The apparatus of claim 15 , wherein the package substrate includes an additional resistor embedded in the package substrate, and the additional die includes additional buffer circuits and an additional multiplexor circuit, the additional buffer circuits including output nodes coupled to the conductive contacts of the package substrate, the additional multiplexor circuit including first nodes coupled to respective output nodes of the additional buffer circuits, and a second node coupled to the additional resistor.

18. The apparatus of claim 15 , wherein one of the die and the additional die includes a processor.

19. An electronic system comprising:
a circuit board including conductive paths;
a package substrate attached to the circuit board and coupled to the conductive paths, the package substrate including conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate; and
a die coupled to the conductive paths of the package substrate through conductive bumps, the die including buffer circuits and a calibration module coupled to the buffer circuits, the buffer circuits including output nodes coupled to the conductive bumps, the calibration module coupled to the resistor through one of the conductive bumps and configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

20. The system of claim 19 , wherein the buffer circuits are included in a Peripheral Component Interconnect Express (PCIe) interface and a memory interface of the die.

21. The system of claim 19 , wherein the package substrate and the die are part of a system on chip (SoC).

Assignees

• Intel Corp

Inventors

• Shekhar Sameer
• Jain Amit K
• Nukala Pooja

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title