Methods for fabricating semiconductor devices

Patent metadata

Field	Value
Publication number	US-9812552-B2
Application number	US-201514679166-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	Dec 18, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively and partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern. The methods may also include replacing at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with a conductive pattern.

First claim

What is claimed is:

1. A method of forming an integrated circuit device, the method comprising:
forming a gate structure on a substrate, the gate structure extending longitudinally in a first direction in plan view;
forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively;
partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern; and
replacing at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with a conductive pattern,
wherein the conductive pattern has a first width in the first direction adjacent the gate structure and has a second width in the first direction adjacent a medial point of the conductive pattern along a second direction that is a transverse direction of the gate structure, and the first width is greater than the second width.

2. The method of claim 1 , further comprising forming a source/drain region in the substrate, the conductive pattern being electrically connected to the source/drain region.

3. The method of claim 2 , wherein the conductive pattern contacts the source/drain region.

4. The method of claim 2 , further comprising forming an insulating isolation pattern in the substrate, the second sacrificial pattern overlying the insulating isolation pattern.

5. The method of claim 2 , wherein:
forming the first and second sacrificial patterns comprises forming the first sacrificial pattern having an upper surface disposed lower than an upper surface of the gate structure; and
partially replacing the first sacrificial pattern with the first insulating pattern comprises forming a portion of the first insulating pattern overlying the upper surface of the first sacrificial pattern.

6. The method of claim 5 , further comprising replacing the gate structure with a metal gate structure comprising a metal gate electrode before replacing the at least some of the portion of the first sacrificial pattern with the conductive pattern.

7. The method of claim 6 , wherein:
forming the first and second sacrificial patterns comprises forming the first and second sacrificial patterns comprising a non-insulating material comprising silicon; and
partially replacing the first sacrificial pattern with the first insulating pattern and replacing the second sacrificial pattern with the second insulating pattern comprises partially removing the first sacrificial pattern such that the portion of the first sacrificial pattern remains on the substrate and removing the second sacrificial pattern using an wet etching process.

8. The method of claim 7 , further comprises forming an etch stopping layer between the substrate and the first and second sacrificial patterns, wherein:
the first and second sacrificial patterns comprise polysilicon; and
an etchant of the wet etching process comprises ammonia (NH 3 ).

9. The method of claim 1 , wherein replacing the at least some of the portion of the first sacrificial pattern with the conductive pattern comprises entirely replacing the portion of the first sacrificial pattern that remains in the first insulating pattern with the conductive pattern.

10. The method of claim 1 , wherein:
the conductive pattern comprises a contact plug that is electrically connected to the substrate; and
the contact plug has a non-uniform width in the first direction of the gate structure, the width of the contact plug monotonically decreasing in the second direction from adjacent the gate structure to proximate a medial point of the contact plug along the second direction.

11. The method of claim 10 , wherein the contact plug has a U-shaped sidewall having a base and legs that extend from the base away from the contact plug in plan view.

12. The method of claim 1 , wherein:
forming the gate structure comprises forming a first gate structure on the substrate;
replacing the at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with the conductive pattern comprises removing the at least some of the portion of the first sacrificial pattern thereby forming a first opening in the first insulating pattern and forming a first conductive pattern in the first opening; and
the method further comprises:
forming a second gate structure on the substrate;
forming a third sacrificial pattern on a side of the second gate structure;
replacing the third sacrificial pattern with a third insulating pattern;
forming a second opening in the third insulating pattern; and

forming a second conductive pattern in the second opening concurrently with forming the first conductive pattern in the first opening.

13. A method of forming an integrated circuit device, the method comprising:
forming a first gate structure and a second gate structure on a substrate, the first and second gate structures extending longitudinally in a first direction in plan view; and
forming a conductive pattern and an insulating pattern between the first and second gate structures, the conductive pattern being wider adjacent the first and second gate structures compared to between the first and second gate structures,
wherein the conductive pattern has a first width in the first direction adjacent the first and second gate structures and has a second width in the first direction between the first and second gate structures, and the first width is greater than the second width.

14. The method of claim 13 , wherein the conductive pattern has a curved sidewall having a base and legs that extend from the base away from the conductive pattern in plan view.

15. The method of claim 13 , further comprising forming a source/drain region in the substrate between the first and second gate structures, the conductive pattern being electrically connected to the source/drain region.

16. The method of claim 15 , wherein the conductive pattern contacts the source/drain region.

17. The method of claim 13 , further comprising:
forming a sacrificial pattern between the first and second gate structures, the sacrificial pattern comprising a non-insulating material comprising silicon;
partially replacing the sacrificial pattern with the insulating pattern such that a portion of the sacrificial pattern remains on the substrate; and
replacing at least some of the portion of the sacrificial pattern with the conductive pattern.

18. The method of claim 17 , wherein:
forming the sacrificial pattern between the first and second gate structures comprises forming the sacrificial pattern in a recess defined by the first and second gate structures, the sacrificial pattern being recessed toward the substrate with respect to upper surfaces of the first and second gate structures; and
partially replacing the sacrificial pattern with the insulating pattern comprises partially removing the sacrificial pattern such that the portion of the sacrificial pattern remains on the substrate and forming the insulating pattern in the recess and on the portion of the sacrificial pattern.

19. The method of claim 17 , further comprising replacing the first and second gate structures with a first metal gate structure and a second metal gate structure, respectively before replacing the at least some of the portion of the sacrificial pattern with the conductive pattern, each of the first and second metal gate structures comprising a me

Assignees

• Jun Hwi-Chan
• Shin Heon-Jong
• Jang Jae-Ran
• Samsung Electronics Co Ltd

Inventors

• Jun Hwi-Chan
• Shin Heon-Jong
• Jang Jae-Ran

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10D64/01352

  with sacrificial oxide · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title