Tungsten gates for non-planar transistors

Patent metadata

Field	Value
Publication number	US-9812546-B2
Application number	US-201715401965-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Sep 30, 2011
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a fin having a source and a drain, wherein the fin comprises silicon;
a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises:
a gate dielectric on the fin, wherein the gate dielectric comprises hafnium, silicon, and oxygen;
an NMOS gate electrode on the gate dielectric, wherein the NMOS gate electrode comprises:
a first layer on the gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon;
a second layer on the first layer, wherein the second layer comprises titanium; and
a third layer on the second layer, wherein the third layer comprises tungsten;

sidewalls on opposing sides of the NMOS gate electrode;
a capping structure over the NMOS gate electrode, wherein the capping structure comprises silicon and nitrogen;
a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen; and
a contact extending through the dielectric layer to one of the source and the drain.

2. The integrated circuit (IC) structure of claim 1 , wherein the first layer comprises between about 20 to 40% by weight aluminum, between about 30 to 50% by weight titanium, and between about 10 to 30% by weight carbon.

3. The integrated circuit (IC) structure of claim 1 , wherein the first layer comprises a conformal layer.

4. The integrated circuit (IC) structure of claim 1 , wherein the second layer comprises a conformal layer.

5. The integrated circuit (IC) of claim 1 , wherein the capping structure comprises silicon nitride.

6. The integrated circuit (IC) of claim 1 , wherein the dielectric layer comprises silicon oxide.

7. A method of fabricating an integrated circuit (IC) structure, comprising:
forming a fin, wherein the fin comprises silicon;
forming a sacrificial transistor gate on the fin;
depositing a sidewall dielectric material layer over the sacrificial transistor gate and the fin;
forming transistor gate sidewalls from a portion of the sidewall dielectric material layer, wherein the transistor gate sidewalls are on opposing sides of the sacrificial non-planar transistor gate;
forming a source in the fin on one side of the sacrificial transistor gate;
forming a drain in the fin on an opposing side of the sacrificial transistor gate;
removing the sacrificial transistor gate to form a gate trench between the transistor gate sidewalls, wherein a portion of the fin is exposed;
forming a transistor gate in the gate trench, comprising:
forming a gate dielectric on the fin, wherein the gate dielectric comprises hafnium, silicon, and oxygen;
forming an NMOS gate electrode on the gate dielectric, wherein forming the NMOS gate electrode comprises:
forming a first layer on the gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon;
forming a second layer on the first layer, wherein the second layer comprises titanium; and
forming a third layer on the second layer, wherein the third layer comprises tungsten;

removing a portion of the NMOS gate electrode to form a recess between the transistor gate sidewalls;
forming a capping structure within the recess, wherein the capping structure comprises silicon and nitrogen;
forming a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen; and
forming a contact extending through the dielectric layer to one of the source and the drain.

8. The method of claim 7 , wherein forming the first layer comprises the first layer comprising between about 20 to 40% by weight aluminum, between about 30 to 50% by weight titanium, and between about 10 to 30% by weight carbon.

9. The method of claim 7 , wherein forming the first layer comprises forming a conformal layer first layer.

10. The method of claim 7 , wherein forming the second layer comprises forming a conformal layer second layer.

11. The method of claim 7 , wherein forming the capping structure comprises forming a silicon nitride capping structure.

12. The method of claim 7 , wherein forming the dielectric layer comprises forming a silicon oxide dielectric layer.

Assignees

• Intel Corp

Inventors

• Pradhan Sameer S
• Bergstrom Daniel B
• Chun Jin-Sung
• Chiu Julia

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic